BeginnerQuestion 91 of 95Source: Synopsys PrimeTime User Guide: Design Rule Constraint Checking

What is a DRC violation in timing signoff, and how is it different from a setup or hold violation?

From PDVerse STA Mentor Guide · pdVerse Mentor Guide

By Tabish Iqbal · 9+ Years VLSI Physical Design Experience

Short Answer

A DRC (design rule constraint) violation happens when a signal's own physical limit is broken — its transition time is too slow, or its driven capacitance too high — regardless of any clock relationship. A setup or hold violation is always about a signal arriving too late or too early against a specific clock edge. A path can pass every setup and hold check and still fail a DRC limit, and vice versa.

A driver cell feeding 40 flop loads with the transition-time waveform slowing visibly past a marked max_transition limit line, contrasted with a separate clean setup-path timing diagram beside it. — Technical Reference DiagramWhat is a DRC violation in timing signoff, and how is it different from a setup or hold violation?

Technical Explanation

The two failure types are checked by the same tool but come from completely different physical concerns.

set_max_transition (SDC) and a similar max capacitance limit define the DRC checks: a signal's rise/fall time or driven load must stay under a set ceiling.
These limits exist because a cell's library timing model (LIB) is only accurate within a certain slew and load range — outside it the model itself becomes unreliable, not just slow.
Setup and hold checks instead compare one signal's arrival time against another signal's required time at the same flip-flop, driven entirely by the clock period and any exceptions on that path.
A wire can have a perfectly fine setup slack and still violate max_transition, if it is driving far more load than its driver was sized for.
report_constraint (PT) reports both families in the same summary, but they need different fixes: a DRC violation calls for a bigger driver or a split load, not a changed clock relationship.
Signoff needs both families clean at once — zero setup/hold violations with many DRC violations left is not considered timing-clean.

Common Mistake

The Trap: treating a max_transition violation like a setup violation and trying to fix it by changing the exception structure or path grouping.

That approach does nothing, because DRC limits are per-signal, not per-path-relative-to-clock — no exception command changes a slew or a load.
The actual fix is almost always upsizing the driving cell or adding a buffer to split a heavy net, the same toolkit ECO uses for setup and hold.

Follow-up Question & Model Response

Can a DRC violation on one net actually cause a setup or hold violation somewhere else in the design?

Candidate Model Response: Yes — this is the usual way the two failure types connect. A net with excessive load produces a slower transition, and that slow transition adds extra delay to every downstream gate it drives, which can push a previously passing setup path into a violation. Fixing the DRC violation first, by upsizing the driver or splitting the load, often improves the downstream setup slack as a side effect. This is one reason signoff flows typically clear DRC violations before spending ECO effort on the remaining setup and hold numbers.

Practical Example

A clock-gating cell drives 40 flops directly, past its library's recommended fanout. report_constraint (PT) shows it clean on setup and hold but VIOLATED on max_transition at 0.62ns against a 0.4ns limit. Splitting the load with two buffers fixes the DRC violation and recovers 35ps of setup slack on the slowest downstream path.

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