What is the difference between a flat and a hierarchical timing run?
From PDVerse STA Mentor Guide ยท pdVerse Mentor Guide
Short Answer
A flat timing run loads a design's entire netlist into one analysis, with every gate and wire visible to the tool at once, regardless of which block it belongs to. A hierarchical run instead analyzes some blocks using compact stand-in models โ an extracted timing model or a HyperScale boundary model โ instead of their full netlists, trading a small amount of representational detail for a large reduction in memory and runtime.
Technical Explanation
Both approaches aim to answer the same question โ does the design meet timing โ but they differ in how much of the design the tool actually has to hold in memory at once to answer it.
- A flat run treats hierarchy as organizational only. Blocks and sub-blocks exist in the netlist's naming and structure, but the tool sees straight through every boundary โ a path can be traced gate by gate from anywhere to anywhere, because nothing is abstracted away.
- A hierarchical run replaces some blocks with models. An extracted timing model (ETM) or a HyperScale block model stands in for a block's internals, so paths crossing that block use the model's input-to-output arcs instead of tracing through real gates.
- Flat is simpler to reason about but costs more. There is no question of whether a boundary model is stale or accurately built, because there are no boundary models โ but the memory and runtime cost scales with the entire design's size, all at once.
- Hierarchical is cheaper but adds a dependency. Analysis cost drops significantly, but the results are only as accurate as the block models in use, which means a process for keeping those models current has to exist alongside the analysis itself.
- The choice is not all-or-nothing. A design can be partially flat, with only a few large or especially stable blocks represented by models, matching the approach to which blocks actually need the memory savings.
- Why it matters: as designs grow, a fully flat run eventually becomes impractical, and hierarchical becomes not an optimization but the only way to get a signoff-quality result in a workable time.
Common Mistake
The Trap: assuming a hierarchical run is inherently less trustworthy than a flat run, and treating flat as the only real signoff-quality option.
- A team insists on a full flat run for final signoff even though every block model in the hierarchical run has been freshly regenerated and verified, spending days of extra compute time on a result that would not meaningfully differ from the hierarchical one.
- The real question is not flat versus hierarchical in the abstract, but whether the specific models a hierarchical run depends on are current and correctly built โ a hierarchical run with fresh, verified models is just as trustworthy as a flat run, at a fraction of the cost.
Follow-up Question & Model Response
Would you ever need to run a flat analysis on a block that normally uses a hierarchical model, even after the model has been verified?
Candidate Model Response: Yes, specifically when debugging a violation whose root cause lives inside that block. The hierarchical model can tell you a path crossing the block has a certain delay, but not which internal gate or net is responsible, since the model has no internal representation at all. I would switch to a full-netlist analysis of just that block to trace the internal path, then return to the model-based view once the issue is understood and fixed.
Practical Example
A top-level SoC signoff run represents its CPU core and memory controller with ETMs, since both are design-complete and stable, while a newly-added accelerator block is analyzed flat, since it is still under active closure and its model would go stale within days. This mixed approach finishes in under 4 hours, versus an estimated 22 hours fully flat, while still giving full visibility into the one block being actively debugged.
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