What does an ETM actually hide, and what timing information does it keep at the block boundary?
From PDVerse STA Mentor Guide ยท pdVerse Mentor Guide
Short Answer
An extracted timing model (ETM) hides everything happening inside a block โ its gates, its internal nets, its internal paths โ and keeps only the input-to-output timing arcs a neighboring block actually needs: how long a signal takes to cross the block, and what capacitance or drive strength it presents at each boundary pin. It is built so a top-level run can time paths that pass through the block correctly, without ever loading the block's real netlist.
Technical Explanation
The whole point of an ETM is to answer exactly what a top-level analysis needs from a block and nothing more, since loading every block's full netlist is what makes flat, hierarchical analysis expensive in the first place.
- What is hidden: the internal netlist. Every gate, every internal net, and every internal timing path inside the block disappears from the model โ the top level never sees them and cannot report on them.
- What is kept: input-to-output timing arcs. For each input pin that can affect an output pin's timing, the model keeps the delay (and, where relevant, delay variation across corners) of that specific path through the block, generated with the
extract_model(PT) command. - What is kept: boundary electrical behavior. Each input pin's model keeps how much capacitance it presents to whatever drives it from outside the block, and each output pin's model keeps its effective drive strength, so a top-level path's delay calculation across the block boundary stays accurate.
- Why the tradeoff is worth it: a top-level run using ETMs for its sub-blocks needs a fraction of the memory a fully flat run would, since dozens of blocks' internal netlists are replaced by compact input-to-output tables.
- What breaks: trying to debug an internal timing problem using only the ETM โ with no internal paths represented, a violation traced inside the block has to be debugged against that block's own full netlist, not the top-level ETM run.
Common Mistake
The Trap: debugging a top-level path's violation by digging into the ETM itself, expecting to find the internal gate or net responsible.
- A designer sees a violating path pass through a sub-block's ETM in a top-level
report_timing(PT) trace and tries to correlate the ETM's arc delay against internal cell delays inside that block. - The ETM has no internal cells to correlate against โ it only has the input-to-output arc as a single number โ so the correct move is switching to the block's own full-netlist timing run to see which internal path actually produces that arc's delay.
Follow-up Question & Model Response
If a block has two different internal paths that both reach the same output pin from the same input pin โ one fast, one slow depending on which mode is active โ how does an ETM represent that?
Candidate Model Response: It depends on how the model was generated. If extracted per mode, using extract_model's per-scenario support, each mode gets its own version of that arc, correctly reflecting whichever path is active. If generated from only a single mode, the arc reflects whichever path was active during extraction, and the other mode's real behavior goes unrepresented โ which is why regenerating ETMs whenever a block's active modes change matters.
Practical Example
A memory controller block has 40,000 internal gates but exposes only 24 input and 18 output pins to the top level. Its ETM, generated with extract_model -output mem_ctrl_etm (PT), reduces the block to 432 input-to-output arcs plus per-pin capacitance and drive-strength data โ a few hundred kilobytes, versus the multi-hundred-megabyte netlist the full block would otherwise need at the top level. A path that crosses two of its pins times correctly using just that one arc, with no internal gate ever loaded.
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