AdvancedQuestion 25 of 63Source: Synopsys PrimeTime User Guide: Checking the Constraints

What timing checks does PrimeTime run besides setup and hold, and why can all of them pass while one is silently skipped?

From PDVerse STA Mentor Guide · pdVerse Mentor Guide

By Tabish Iqbal · 9+ Years VLSI Physical Design Experience

Short Answer

Beyond the setup and hold check, PrimeTime also verifies recovery and removal times on asynchronous set/reset pins, minimum pulse width and minimum period on clocks, and design-rule limits like maximum transition and maximum capacitance. Any one of these can be skipped entirely if the object it applies to was never constrained, so a clean setup/hold report does not by itself mean every check actually ran.

A checklist diagram showing PrimeTime's full check set - setup, hold, recovery, removal, min pulse width, min period, max transition, max capacitance - with the setup/hold boxes shown green and a check_timing warning box highlighting 4 unclocked register pins that none of the other checks ever touched — Technical Reference DiagramWhat timing checks does PrimeTime run besides setup and hold, and why can all of them pass while one is silently skipped?

Technical Explanation

Setup and hold are only two of several sequential checks. PrimeTime also enforces recovery and removal time - the asynchronous-pin equivalent of setup and hold - for reset and set pins on flip-flops.
Minimum pulse width and minimum period are clock-quality checks. They confirm the clock waveform itself, high time, low time, and period, stays wide enough for the library cells to switch reliably; set_min_pulse_width (SDC) can tighten or loosen the library default.
Design rule checks (DRC) are separate from timing checks entirely. Maximum transition (set_max_transition (SDC)) and maximum capacitance (set_max_capacitance (SDC)) limit slew and load, not arrival time versus required time - a path can meet setup and hold and still violate a DRC limit.
check_timing (PT) is the tool that finds gaps before any of this runs. It reports register clock pins with no clock, latches that fan out to themselves, combinational feedback loops, and generated clocks with broken source paths - problems that would otherwise leave a check silently un-run.
A missing check produces no violation, because there is nothing to violate. If a reset pin was never given a recovery/removal relationship, PrimeTime does not report 0 violations for it - it reports nothing, because the check was never set up.
The fix is to read check_timing's warnings, not just its absence of errors. Warnings do not always mean a real design problem, but each one names a check that might not be running the way you assume.

Common Mistake

Assuming a summary of "0 setup violations, 0 hold violations" means every timing check on the chip passed.
Recovery/removal, min pulse width, and DRC checks (max transition, max capacitance) run independently and can be skipped or misconfigured without ever touching the setup/hold count.
Cost: a reset pin with no recovery/removal check, or a net that never got a max transition limit, ships unverified even though the headline numbers look perfect.

Follow-up Question & Model Response

If check_timing reports "4 register clock pins with no clock" but the setup/hold summary still shows 0 violations, what does that actually mean for signoff?

Candidate Model Response: It means those four registers' data paths were never included in the setup/hold count at all, because PrimeTime cannot check a path whose capturing clock does not exist. The zero-violation summary is accurate for every path it did evaluate, but it is silent about the paths it skipped. I would find those four clock pins, confirm whether they are genuinely unclocked test or scan logic or a real oversight, and either add the missing create_clock (SDC) or tie them to a fixed value with set_case_analysis (SDC) before treating the report as complete.

Practical Example

Running check_timing (PT) on a mixed-signal SoC returns: "Warning: There are 4 register clock pins with no clock", "Warning: There are 2 level-sensitive latches which fanout to themselves", and "Warning: There are 6 timing loops in the design". The setup/hold summary for the same run shows zero violations, because none of those seven flagged structures were ever part of a checked path. Tracing the four unclocked pins finds a debug-only shift register that a synthesis script forgot to tie to the scan clock; left as-is, it would tape out with an unconstrained, unverified path sitting right next to fully signed-off logic.

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