Level 3 · PrimeTime Analysis & Debugging

Advanced STA Interview Questions

Analyze PrimeTime-specific precedence, annotation, variation, constraints, and clock-network behavior in realistic signoff scenarios.

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Analyze PrimeTime-specific precedence, annotation, variation, constraints, and clock-network behavior in realistic signoff scenarios.

  1. 12 A team proposes leaving clocks ideal (skipping propagated timing) post-CTS to save runtime near a deadline. How do you respond?Advanced · Refuse it. Ideal clocks post-CTS ignore the real clock-tree latency and skew, so they silently mis-time every path in the domain - especially hold, which is skew-dominated. Solve runtime with parallelism and resources instead.
  2. 16 Why does setting only -setup 2 create a hold problem? Walk the edges.Advanced · Because hold checks are derived from the valid setup relationship. Moving the setup capture edge from t=10 to t=20 drags the implied hold check from t=0 to t=10, demanding a full extra cycle of data hold the hardware never needs.
  3. 23 How does on-chip variation (OCV) fundamentally change the setup and hold analysis?Advanced · OCV derates parts of the path differently to build a worst case: for setup the data path and launch clock slow while the capture clock is early-derated; for hold the reverse. CRPR then credits back the pessimism double-counted on the shared clock path.
  4. 01 Explain the precedence interaction when an explicit -sms_scenarios option and an active push_sms_scenario context both apply to a command.Advanced · Explicit references have the highest precedence, so the command's own -sms_scenarios wins and the pushed context is ignored entirely for that command. get_current_sms_scenario still reports the pushed context, but it has no effect on the explicitly scoped command.
  5. 02 Why is report_ocvm -type pocvm -cell_delay -list_not_annotated an important pre-signoff check, and what does a missing cell imply?Advanced · It lists cells with no POCV coefficient or distance data, which fall back to zero variation. Any path through such a cell has under-modeled spread, so its corner is optimistic - a silent hole that can hide a real violation behind a normal-looking report.
  6. 03 A design has both set_annotated_delay on some arcs and a full SPEF read. How does PrimeTime resolve the overlap, and what's the debugging implication?Advanced · Annotated delays win. set_annotated_delay is tier 1 and read_parasitics detailed parasitics are tier 3, so on any arc where both apply the annotated delay is used and the SPEF-derived delay for that arc is ignored.
  7. 04 Why is a per-cell IR-drop annotation treated as uncorrelated with the main rail, and what's the consequence?Advanced · Because a local IR drop is a physically independent droop - one instance's grid sagging says nothing about another's - so PrimeTime compares the full worst-case difference across the annotation instead of assuming driver and load track together.
  8. 05 Derive why MIS is scoped to hold and not setup, using the two NAND switching directions.Advanced · For a low-to-high output the parallel pull-ups make multi-input switching faster, and a hold check uses min delay, so ignoring it would be optimistic. The high-to-low direction slows the cell, which affects setup, but setup paths are long enough that one gate is negligible.
  9. 06 How does PrimeTime model and analyze clock networks, including latency and uncertainty?Advanced · PrimeTime propagates a defined clock waveform through the network to get each register's latency -source plus network - derives skew from latency differences, and adds clock uncertainty for jitter and margin on top, using ideal latency pre-CTS and propagated clocks post-CTS.
  10. 07 Explain the interaction between CCS receiver modeling and max-transition/max-capacitance DRC characterization.Advanced · CCS adds receiver_capacitance1/2 and driver tables, so safe max_capacitance is the lowest maximum load index across all of them and safe max_transition the lowest maximum slew index across NLDM, CCS driver and receiver_capacitance2. Otherwise DRC passes while delay calc extrapolates.
  11. 08 Explain the trip from a StarRC multicorner GPD to a single-corner PrimeTime annotation, and why multicorner extraction is worth it.Advanced · StarRC with SIMULTANEOUS_MULTI_CORNER: YES extracts several corners in one run into a multicorner GPD; PrimeTime picks one with set_app_var parasitic_corner_name <corner> then reads it. It pays off because the expensive geometric processing is done once for all corners.
  12. 09 Explain the interaction between POCV and clock reconvergence pessimism removal on a clock path - do they double-count?Advanced · No - they correct different artifacts. CRPR removes the double-count on the clock segment shared by launch and capture; POCV graph-merging removal removes the stochastic-max inflation at converging gates. Both must be active on a clock path.
  13. 10 Why must all libraries in the scaling groups have CCS noise data specifically, beyond CCS timing?Advanced · Because SMVA is a full signoff feature that includes noise across voltage combinations, and voltage-dependent noise response - crosstalk bumps and immunity - is captured only in the CCS noise models. CCS timing alone cannot produce it.
  14. 11 A path in a switchable domain reports the wrong voltage after a power switch.Advanced · Work outward from the switch: report_power_switch for the On State, report_power_network for the topology through it, report_supply_net on the output net for its voltage states, then report_timing -voltage or pg_pin_info 's voltage_source on the cells.
  15. 13 How do generated clocks interact with source latency, and how does edge-specific source latency propagation work?Advanced · A generated clock's source latency is the master's insertion delay from its origin to the generated clock's source pin. PrimeTime auto-computes it when the master is propagated, and it tracks the master's latencies per edge.
  16. 14 Compare disabling a path with case analysis, set_disable_timing and set_false_path - mechanism, blast radius, and when each is the right tool.Advanced · Case analysis sets a value and structurally kills whatever arcs that value controls; set_disable_timing removes a specific arc or object; set_false_path removes exactly the specified point-to-point paths - and the efficiency ladder prefers them in that order.
  17. 15 Explain why "only internal nets are annotated in SDF" and how that shapes your verification.Advanced · The SDF standard defines INTERCONNECT delays for nets internal to the design; nets on primary I/O ports belong to the environment and are modelled with set_input_delay and set_output_delay . So non-annotation of primary-port nets is correct, not a gap.
  18. 17 Walk through how PrimeTime performs a full timing update internally, from reading data to computing slack.Advanced · It builds the timing graph after link_design, propagates the defined clocks to every register clock pin, calculates arc delays with slew propagation, propagates arrivals forward and required times backward while honoring exceptions, then subtracts them to get slack.
  19. 18 Construct a scenario where forgetting sequential propagation makes a scan-disable silently ineffective.Advanced · Set set_case_analysis 0 [get_ports SCAN_MODE] without enabling sequential propagation on the scan flops and the constant stops at their TE pins: the CP->TI scan arcs stay enabled and the scan chain is still timed, with no warning.
  20. 19 Why might report_mode show a mode ENABLED with Reason default even though you set case analysis intending to disable it?Advanced · Reason default means no mode-selection method actively chose or excluded that mode, so it fell to the group's default state - the tell that your intended set_case_analysis never actually reached the mode's controlling condition.
  21. 20 How do you make PrimeTime remember the source file and line number of each exception, and what's the hard restriction?Advanced · Set sdc_save_source_file_information to true - it defaults to false - and PrimeTime records the file and line of every exception command. The hard restriction is that it can only be changed before any exception has been input.
  22. 21 Explain why set_aocvm_table_group / read_ocvm after a timing update triggers a full update, and the flow implication.Advanced · Derating factors are an input to delay calculation, so changing tables or table groups alters delays on a broad set of arcs and arrivals propagate transitively - there is nothing to patch incrementally, so a full update is forced. Set all variation data before the first update.
  23. 22 How do you decide between set_driving_cell, set_drive, and set_input_transition for accurate boundary modeling?Advanced · Default to set_driving_cell when a library cell can represent the external driver, since it uses the cell's real load-dependent model. Fall back to set_drive for drivers not modeled as a library cell, and use set_input_transition when the slew is load-independent or for tool matching.