How would you decide which clock-related decisions to standardize versus leave to block owners?
From PDVerse PrimeTime STA Interview Guide · pdVerse Mentor Guide
Ten-second Interview Answer
Standardize whatever must be chip-consistent to compose - primary clock definitions, the relationship framework, the modelling methodology, the single-source discipline and verification gates - and delegate block-internal generated clocks, gating details and margin refinements within that framework.
Complete Technical Explanation
The dividing line is whether a decision is chip-shared and has to compose, or purely block-internal. Standardize the chip-level clock definitions - the primary clocks, their periods and waveforms, and the PLL and reference scheme - because these are shared across blocks and must be identical everywhere they appear. Standardize the clock-relationship framework, meaning the chip-level clock groups declaring which domains are synchronous, asynchronous or exclusive, because crossings span blocks and a crossing cannot be asynchronous in one block's view and synchronous in another's. Standardize the clock-modelling methodology as well: ideal versus propagated per stage, uncertainty conventions, jitter as dynamic latency, and generated-clock conventions. Standardize the single clock-constraint source discipline and the verification gates, check_timing clean of unclocked registers and report_clock . Those five things are what make the clocks consistent and composable across the chip. Then delegate the rest to the people with the design knowledge: block-internal generated clocks, such as a divider feeding only that block's logic, defined per the standard conventions; block-internal clock-gating details and their checks; and block-specific uncertainty refinements tuned within the chip-level framework, for example a residual based on that block's own clock tree. None of those cross a boundary, so provided they conform to the standardized definitions and relationships they cannot damage chip-level consistency. The result is block-owner autonomy inside a consistent chip clock framework.
In Pd / Signoff
In practice this is how you write the constraint template. The shared file the block sources contains the primary clocks, the group matrix and the modelling conventions and is read-only to block owners; the block's own file holds its internal create_generated_clock calls, gating checks and residual margin. Review effort then concentrates on the shared file and on whether each block's additions conform.
Common Trap
Standardizing too far and freezing block-internal choices, or too little and leaving the relationship matrix to blocks. The second is the damaging one: independently invented chip-level clocks and crossing declarations conflict only at integration, and they conflict silently, because every block's own run looked clean.
Expect Next
Which clock decisions are legitimately block-internal, and what makes them safe to delegate?
Topic And Primetime Commands
Clocks / Generated Clocks. check_timing, report_clock, create_generated_clockKeep building interview depth
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