Can you give an example of a chip with multiple power domains?
From PDVerse Low-Power Physical Design Mentor Guide · pdVerse Mentor Guide
Definition
A classic multi-voltage example is a top-level domain running at 1.0V that contains three subblocks each running at a different fixed voltage: an ARM926 processor at 1.2V, a DMA block at 1.1V, and an APB peripheral block at 0.9V.
Mentor Explanation
A beginner often assumes 'one chip = one supply voltage,' but real SoCs commonly run different blocks at different voltages to save power where performance isn't needed, while keeping high voltage only where speed is required. Think of it this way: each of those sub-blocks is a 'voltage island' — a region operating at a voltage different from its surroundings — and any signal crossing between islands needs a level shifter.
Example
In this example, ARM926 at 1.2V (performance-critical), DMA at 1.1V, and APB_block at 0.9V (least performance-critical) all sit inside a 1.0V TOP domain, each connected through level shifters at their boundaries.
Why It Matters
This kind of multi-domain partitioning lets designers apply the P ~ V² relationship selectively — giving high voltage (and power) only to the blocks that actually need the performance.
Common Beginner Mistake
PD_MYCHIP—1.0V,always-on PD_CPU 0.9V, always-on PD_COP 1.0V, shutdown retention regs PD_DSP 1.1V or 0.9V externally switched Power Controller (U_PC) PSE • PSE_ACK • ISE • SRE A beginner might assume voltage islands never need any special cells if their voltages are close together, but a level shifter can still be required even between same-voltage domains if buffers are needed along the path through an always-on region.
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