What are disjoint voltage areas, and how does ICC2 derive them automatically?
From PDVerse Low-Power Physical Design Mentor Guide · pdVerse Mentor Guide
Short Answer
A disjoint voltage area is one voltage area made of separate, non-touching shapes, so one power domain can sit in several islands of the floorplan. You use it when the logic of a domain wants to live next to different things, such as two memories or two sets of pads, and one compact shape would stretch the routes to both. ICC2 can derive such shapes with derive_disjoint_voltage_areas_ml (ICC2), a machine-learning feature that reads the netlist, UPF and timing constraints, and you should treat its output as a proposal you check for power, switches and routing, not a finished floorplan.
Technical Explanation
- Definition:
create_voltage_area(ICC2) accepts several shapes, which can be abutted, disjoint or overlapping; cells of the domain may go in any of them. - Placer view: a voltage area acts like an exclusive move bound, so domain cells stay inside its shapes and every other cell stays out of them.
- Why islands: they keep a domain close to each thing it talks to, shortening timing-critical routes that a single compact shape would stretch across the die.
- Cost: nets between islands cross another domain, so they need feedthrough buffering, and each island needs its own switches, straps and secondary PG.
- ML derivation:
derive_disjoint_voltage_areas_ml(ICC2) generates non-overlapping VAs aligned to domain boundaries; it suits flat designs where blocks do not fix VA shapes. - Setup: set
mv.cells.auto_va_set_voltage_file_name(ICC2) so every UPF supply has a voltage; the command can run distributed through-host_options. - Library safety: the tool restores the original design library afterwards, but the guide warns a system failure may leave it unrestored.
Common Mistake
The Trap: Treating the two islands as independent and powering each with its own switch control, because they look like two blocks on the floorplan.
- They belong to one domain with one power state, so the switches in both islands must share control and ack, or one island wakes while the other stays off. Ramp-up and IR checks must also cover both islands together.
- Isolation and retention then see a half-on domain that no strategy or power state describes, and simulation will not model what the silicon does.
Follow-up Question & Model Response
"How do signals get between the two islands of a switchable domain?"
Candidate Model Response: They cross whatever lies between the islands, usually the always-on top area or another domain. ICC2 can buffer them with physical feedthrough buffers using dual-rail cells, or logical feedthrough buffers with punched ports, once create_voltage_area_rule (ICC2) enables it for that VA. The buffer supply must stay valid while the net is used, which is why the tool checks how always-on each supply is. If the route is long and the domain is off most of the time, a single island may be simpler. Decide with timing and area numbers from both floorplans, not by habit.
Practical Example
Design Scenario: (illustrative) PD_VID talks to a left-side ADC interface and a right-side SRAM. A single VA in the middle forced 1.4 mm routes on both sides, and the SRAM read path missed timing by 80 ps. Two islands, VA_VID shape A at the ADC and shape B at the SRAM, cut the worst route to 0.4 mm and closed the SRAM path with 20 ps to spare. The cost: 30 feedthrough buffers on the 64-bit bus between islands, two switch arrays chained on one control, and VDD1p0 straps in both islands. Before committing, the team ran derive_disjoint_voltage_areas_ml on a copy of the flat design, and its suggested islands matched the manual plan within one row of cells. The switches in both islands share one daisy chain started from U_PC, so one ack reports the whole domain on. Numbers are illustrative.
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