How do you implement a multivoltage design hierarchically in ICC2?

Short Answer

You split the flat design and its UPF into blocks, shape the blocks so their voltage areas fit, build top-level straps, and push a PG strategy down to each block. Each block then builds its own PG and secondary PG constraints and is implemented against its block UPF, while the top commits the block constraints and checks everything together. The order matters because each step uses data the previous one produced.

Technical Explanation

• Partition: split_constraints (ICC2) writes block-level constraints and UPF, and commit_block (ICC2) turns the partitions into physical blocks.
• Shape: shape_blocks (ICC2) creates block shapes and the voltage area shapes inside them.
• Top PG: build top straps first, then characterize_block_pg (ICC2) derives the PG strategy each block must follow.
• Block PG: compile_pg (ICC2) builds straps in each block, then you create and commit that block secondary PG constraints.
• Top commit: commit_secondary_pg_placement_constraints -commit_subblocks (ICC2) commits any uncommitted block constraints along with the top ones.
• Consistency: block supply ports and top supplies must connect, or supplies become independent and the system PST grows.
• Block scope: keep block UPF supplies inside the block scope, so the block can be implemented alone without names that only exist at the top.

# [ICC2]  icc2_shell
split_constraints
commit_block
shape_blocks
characterize_block_pg
compile_pg
commit_secondary_pg_placement_constraints -commit_subblocks
report_secondary_pg_placement_constraints -all_blocks
check_secondary_pg_placement_constraints -blocks {BLK_CPU BLK_DSP}
check_mv_design

What To Check

• Each block UPF matches the slice of the top UPF it came from.
• Block voltage areas sit inside their block shapes with guard bands intact.
• Top and block straps line up at the block boundary.
• Block and top secondary PG constraints are all committed.

Healthy, Suspicious & Hard-stop Results

• Healthy (illustrative): Every block reports committed constraints and check_mv_design is clean at the top.
• Suspicious (illustrative): Blocks are clean alone, but the top shows two supply net groups where one was expected.
• Hard stop: Block straps miss the top straps at the boundary, or a block has uncommitted secondary PG constraints at top commit.

What The Interviewer Is Testing

• Can you order the hierarchical MV steps?
• Do you know what the top must re-check after blocks come back?

Follow-up Question & Model Response

"How does the top see a finished block during MV checks?"

Candidate Model Response: Through its block UPF and an abstract or ETM that carries the port supplies. The top needs each block port to have a known related supply, so crossings at the boundary can be checked. save_upf -full_chip -block (ICC2) can also write a full-chip UPF for specific blocks, which helps when a block team needs the surrounding intent. If a port supply is missing, the top treats the crossing as unknown and misses isolation or level shifters.