How does a power switch's control and acknowledgment signal pair work?
From PDVerse Low-Power Physical Design Mentor Guide · pdVerse Mentor Guide
Technical Explanation
A power switch is built with create_power_switch, given an input supply port, an output supply port, and a control port that drives it on or off. The on_state and off_state arguments define, as a boolean function of the control signal, when the output is powered and when it isn't. Optionally the switch can also report back through an ack_port: once the switch has settled into its commanded state, the ack line changes to confirm it, and ack_delay specifies how long after the control changes the acknowledge is expected to be valid.
Architecture-level Reasoning
Real power switches (especially large distributed switch networks) do not turn on instantaneously — there is a rushcurrent-limited ramp before the output rail is truly stable. The control/acknowledge handshake exists so downstream logic (and the power controller itself) knows not to assume the domain is powered just because the control signal was asserted; it waits for the ack.
Step-by-step Walkthrough
1) create_power_switch declares the switch's supply ports and control port, with -on_state {name supply_net expr} and off_state {name expr} describing exactly when the output is up or down. 2) Adding a control sense and acknowledge with control_sense high -ack_port {SLEEPO PWRCTL_ACK} -ack_delay {SLEEPO 1} tells the tool that once the control (sleep) signal is driven, the acknowledge output SLEEPO is expected valid after the specified delay. 3) In the Mychip example, PD_COP_SW is built with -control_port {SLEEP U_PC/PSE} and -ack_port {SLEEPOUT U_PC/ PSE_ACK} -ack_delay {SLEEPOUT 10}, with -on_state {SW_on VDDG ! SLEEP} and -off_state {SW_off SLEEP} — so the switch is on when SLEEP is deasserted and off when SLEEP is asserted, and the power controller only trusts the domain state once PSE_ACK has responded.
Command
create_power_switch PD_COP_SW -domain PD_COP -input_supply_port
{VDDG VDD1p0} -output_supply_port {VDD VDD1p0_SW} -control_port
{SLEEP U_PC/PSE} -ack_port {SLEEPOUT U_PC/PSE_ACK} -ack_delay
{SLEEPOUT 10} -on_state {SW_on VDDG !SLEEP} -off_state {SW_off
SLEEP}Switch-by-switch
-input_supply_port {port net}: names the always-on input rail
feeding the switch. -output_supply_port {port net}: names the
switched output rail. -control_port {port net}: the control
signal, here tied to the power controller's PSE output. -ack_port
{port net}: the acknowledge output, here tied to PSE_ACK. ack_delay {port value}: the expected delay before the acknowledge
is valid after a control change. -on_state / -off_state {name
expr}: the boolean condition, in terms of the control signal,
under which the output supply is on or off.Expected Result
A power switch whose output rail correctly tracks the commanded on/off state, and whose acknowledge output can be used by the power controller (and by verification) to confirm the domain has actually reached the commanded state before dependent logic proceeds.
Possible Implementation Error
Wiring the control port's sense backwards relative to the on_state/ off_state expressions (e.g. treating SLEEP as active-low when the power controller drives it active-high), so the switch turns on and off at the wrong times relative to the intended sequencing.
Likely Tool / Clp Warning
There is no specific error code documented for a control-sense mismatch on power switches; the practical symptom would be an on_state/off_state expression that never matches the actual driven polarity.
Root Cause
on_state/off_state are plain boolean expressions over the control port — the tool has no independent notion of 'correct' polarity beyond what you write, so a sense mismatch is a pure specification error.
Debugging Sequence
1) Confirm the actual driven polarity of the control signal from the power controller RTL/UPF (e.g. U_PC/PSE). 2) Compare against the on_state/off_state expressions in create_power_switch. 3) Verify the ack_port's expected delay against the real switch-cell datasheet/library timing if available. A control-sense or ack-timing mismatch on a power switch is a functional power-sequencing bug that must be resolved before power-intent signoff.
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