What is the architectural difference between header and footer power switches, and when would each be used?
From PDVerse Low-Power Physical Design Mentor Guide · pdVerse Mentor Guide
Technical Explanation
A header switch sits between the power rail and the power supply pins of the power-down domain, cutting VDD to the domain. A footer switch instead sits on the ground side, cutting the connection between the domain's ground pins and the ground rail. Both accomplish the same goal — removing the supply path to shut a domain's leakage down — but they differ in which rail they interrupt.
Architecture-level Reasoning
The choice between header and footer is a library/technology decision driven by which switch device (typically a PMOS header vs an NMOS footer) gives better on-resistance and area for the process, and by CPF's own explicit two-stage switch modeling, which lets a switch be characterized in stages with different onresistance values for coarse and fine control. HEADER SWITCH VDDG (always-on) switch NSLEEPIN VDD (switched) domain logic FOOTER SWITCH domain logic VSS (switched) switch SLEEPIN VSSG (always-on)
Step-by-step Walkthrough
1) In UPF, the physical distinction between header and footer is realized by which supply port (input_supply_port on the power side vs the ground side) the switch is inserted into, mapped later to a real header or footer library cell via map_power_switch. 2) CPF makes the header/footer choice an explicit modeling parameter: define_power_switch_cell -type header|footer, and CPF further supports two-stage switches with stage_1_enable/-stage_1_output and -stage_2_enable/stage_2_output, each carrying its own -stage_1_on_resistance/stage_2_on_resistance example values (e.g. 200 and 10) and an enable_pin_bias.
Command
define_power_switch_cell -cells -ground -power_switchable power -stage_1_enable -stage_1_output -type header stage_2_enable -stage_2_output -stage_1_on_resistance 200 stage_2_on_resistance 10 -enable_pin_bias 0:0.2Switch-by-switch
-type header|footer: declares whether this switch cell interrupts
the power rail (header) or the ground rail (footer). stage_1_enable/-stage_1_output, -stage_2_enable/-stage_2_output:
define a two-stage switch's enable and output pins for coarse/
fine sequencing. -stage_1_on_resistance/-stage_2_on_resistance:
example on-resistance values for each stage (given as
illustrative numbers, not a general IR-drop formula). enable_pin_bias: bias window for the enable pin.Expected Result
A switch topology (header or footer) that correctly interrupts the intended rail for the shutdown domain, mapped to the appropriate library switch cell.
Possible Implementation Error
Mapping a domain's switch strategy to a footer cell in a library where only header cells are characterized for that voltage, causing map_power_switch to fail to find a matching library cell.
Likely Tool / Clp Warning
This topic is not covered in enough depth here to give a fully reliable answer regarding a specific error code for a header/footer library mismatch at map_power_switch time.
Root Cause
The header/footer type is a property of the specific library switch cell; mismatching the UPF-declared switch type against what the library actually offers leaves no valid cell for the mapping step.
Debugging Sequence
1) Check which switch types (header/footer) the target library actually provides via its Liberty definitions. 2) Confirm the create_power_switch/map_power_switch statements request a type the library supports. 3) For CPF flows, verify define_power_switch_cell's -type matches the real cell. A switch type unavailable in the library is a synthesis/ mapping blocker that must be fixed before implementation can proceed.
Continue learning free
Get a practical low-power chapter
Receive the existing “Low Power and Multivoltage Fundamentals” PDF chapter and its download link by email.
Continue practising