What is the rush-current problem during power-up, and how do daisy-chain vs. parallel switch-enable sequencing strategies address it?
From PDVerse Low-Power Physical Design Mentor Guide · pdVerse Mentor Guide
Definition
The rush-current (inrush-current) problem is the large, momentary current surge that occurs when a power-gated domain's virtual rail is reconnected to the always-on supply, because the domain's decoupling and load capacitance must charge up from roughly 0V to full Vdd almost instantly if every sleep transistor in the domain turns on simultaneously — and that surge can cause a damaging IR-drop droop on the shared always-on rail, potentially disturbing every other domain sharing that rail.
Mentor Explanation
If all of a domain's sleep transistors (which may number in the dozens or hundreds across a large block) switch on at exactly the same instant, the combined inrush current spikes far above the domain's normal operating current, and that spike has to be supplied by the shared always-on power grid — which wasn't sized for an instantaneous transient that large, so the whole chip's supply rail can sag momentarily, potentially causing setup violations or even functional glitches in unrelated, still-active domains sharing that same grid. Sequencing strategies solve this by not turning every sleep transistor on at once: a daisy-chain sequence turns sleep transistors on one after another (or in small successive groups) with a deliberate small delay between each stage, so the domain's capacitance charges up gradually and the peak instantaneous current stays bounded, at the cost of a longer total wake-up time; a parallel (all-at-once) sequence turns every switch on simultaneously for the fastest possible wake-up, but only when the domain is small enough, or the always-on grid is over-provisioned enough, that the resulting inrush current is acceptable without a droop. The mother-daughter (staged) switch configuration is one concrete circuit-level way to implement a daisy-chain-style sequence: a small "mother" switch turns on first to begin charging the rail gently, and only once the rail has partially risen does the much larger "daughter" switch array turn on to finish the job quickly without the full inrush of a single one-shot turn-on.
Example
A large GPU domain waking from full shutdown to active use is a classic rush-current risk case — if its many sleep-transistor fingers all enabled simultaneously, the resulting current spike could sag the always-on rail enough to cause a nearby always-on control block (perhaps managing the very domain that's waking up) to briefly see undervoltage, which is exactly the kind of interacting failure daisy-chain or mother-daughter sequencing is designed to prevent.
Why It Matters
This is a chip-level power-integrity concern, not just a power-saving one — an under-sequenced wake-up can cause a functional failure in a domain that had nothing to do with the one waking up, purely through a shared-rail IR-drop droop, which makes rush-current sequencing a signoff-relevant design decision (verified via dynamic IR-drop/power-integrity analysis), not an optional refinement.
Command
# Conceptual staged-enable sequencing (control-logic concept, not literal UPF syntax):
enable_stage[0] = power_up_request;
for i in 1..N-1:
enable_stage[i] = delay(enable_stage[i-1], stagger_delay);
# each stage gates a successive group/finger of sleep transistors,
# bounding peak inrush current at the cost of total wake-up latencyCommon Beginner Mistake
Assuming that once a design has isolation cells and retention registers in place, the domain is safe to power up however is fastest (all switches at once), without separately analyzing inrush current. Isolation and retention address functional correctness of signals crossing the boundary; rush-current sequencing addresses a completely separate physical/power-integrity concern (shared-rail IR-drop) that can cause a functional failure even when every isolation and retention strategy is implemented correctly.
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