After a late ECO, isolation or level shifters are missing. What's your triage flow?
From PDVerse Low-Power Physical Design Mentor Guide · pdVerse Mentor Guide
Short Answer
A late ECO can add ports and domain crossings that no isolation or level-shifter strategy was written for, so the cells are never inserted. Triage in a fixed order: find every new crossing with check_mv_design (ICC2), fix the power intent first, insert cells with create_mv_cells (ICC2), then rerun check_lp -stage design (VCLP) as the independent signoff check.
Technical Explanation
- New crossings: an ECO that reroutes a net or punches a hierarchical port can create a domain crossing the original UPF never described.
- Element-based strategies name ports one by one, so a newly punched port is not covered; strategies implied by the domain name pick it up automatically.
- Control ports: ICC2 derives -no_isolation on newly punched save, restore, switch and isolation control pins, which can hide a real violation on those paths.
mv.cells.smart_derive_iso_strategy_on_new_control_ports(ICC2) checks for a violation first, but the guide limits it to retention control pins today.- ECO buffers:
add_buffer_on_route(ICC2) inserts single-rail buffers; one whose domain supply differs from its driver or load needsfix_mv_design -buffer(ICC2). - Order matters:
create_mv_cells(ICC2) inserts only what a UPF strategy asks for, so fix the strategy before you insert cells. - What breaks: a missing isolation cell floats an always-on input when PD_COP is off; a missing low-to-high level shifter leaks crowbar current and weakens the logic high.
# [UPF] UPF command, run in icc2_shell
set_isolation ISO_COP_OUT -domain PD_COP -update -elements {U_COP/dbg_valid}
# [ICC2] icc2_shell
check_mv_design -isolation -level_shifter -max_message_count all
check_mv_design -isolation -objects {U_COP/dbg_valid}
report_mv_path -isolation -pin U_COP/dbg_valid
create_mv_cells
check_mv_design
save_upf mychip_eco.upf
# [VC LP] vc_static_shell
check_lp -stage design
report_violations -app LPWhat To Check
- Every port the ECO added or reconnected, with its driver domain and load domain.
- Each new crossing out of a switchable domain has a matching isolation strategy, or a deliberate -no_isolation.
- New low-to-high crossings (0.9 V PD_CPU into 1.0 V PD_MYCHIP) have level shifters.
- ECO buffers on crossings run from a supply that stays on whenever their load is on, or are dual-rail.
- The saved UPF matches the netlist that PT and VC LP will read.
Command Checks & Actions
set_isolation ISO_COP_OUT -domain PD_COP -update -elements {U_COP/dbg_valid}Add the new port to the existing element-based strategy
check_mv_design -isolation -level_shifter -max_message_count allList every isolation and level-shifter violation without the default 20-per-type cap
check_mv_design -isolation -objects {U_COP/dbg_valid}Recheck isolation only on paths through the ECO port
report_mv_path -isolation -pin U_COP/dbg_validShow the isolation path through the ECO port, its supplies and any applied strategy
create_mv_cellsInsert the isolation and level-shifter cells the updated strategies require
save_upf mychip_eco.upfWrite the updated power intent for PT and VC LP
check_lp -stage designIndependent static check of the post-ECO netlist against the UPF
report_violations -app LPList remaining LP violations, such as ISO_INST_MISSING
Healthy, Suspicious & Hard-stop Results
- Healthy (illustrative):
check_mv_designand check_lp -stage design both report zero isolation and level-shifter errors after create_mv_cells. - Suspicious (illustrative): ICC2 is clean but VC LP reports ISO_STRATEGY_MISSING on the new port, so the two tools read different UPF (save_upf was skipped).
- Hard stop: report_violations -app LP shows ISO_INST_MISSING on a PD_COP output that reaches PD_MYCHIP.
Common Mistake
The Trap: Hand-instantiating a library isolation cell on the new port without touching the UPF.
check_mv_design(ICC2) warns that the cell is not associated with any isolation strategy (MV-071), and every tool reading the old UPF still sees an unprotected crossing.
What The Interviewer Is Testing
- Do you know how ECOs escape the UPF: new ports, element-based strategies and single-rail ECO buffers?
- Do you fix the power intent before inserting cells, and re-verify in a second tool?
Follow-up Question & Model Response
"The ECO added a buffer on a PD_COP-to-PD_MYCHIP net with add_buffer_on_route. What can go wrong?"
Candidate Model Response: The command inserts single-rail buffers, so the buffer takes the primary supply of whatever domain it lands in. If that supply differs from its driver or load supply, you have a multivoltage violation, and a buffer on VDD1p0_SW dies with PD_COP. Run fix_mv_design -buffer (ICC2) to swap it to a dual-rail cell. If the library has no dual-rail buffers, add -move_within_x or -move_within_y so the tool can move it into a nearby voltage area that has the right supply.
Practical Example
Design Scenario: (illustrative) A timing ECO on MYCHIP punches a new output port U_COP/dbg_valid on U_COP and routes it to a debug mux in PD_MYCHIP. ISO_COP_OUT was written with -elements listing 14 ports, so the 15th is uncovered and no cell is inserted. check_mv_design -isolation flags one error, and report_mv_path -isolation -pin U_COP/dbg_valid shows the path with no applied strategy. Adding the port with set_isolation -update and rerunning create_mv_cells inserts one clamp-0 cell, since dbg_valid is active-high and 0 means idle. Both check_mv_design and check_lp -stage design then report zero isolation errors.
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