Walk through the complete shutdown and wake-up sequence of a switchable domain.

Short Answer

Shutdown runs stop clocks, assert isolation, save state, then switch off and wait for the acknowledge. Wake-up is the mirror: switch on and wait for the acknowledge, restore state, release isolation, then restart clocks, and swapping any two neighbouring steps either corrupts retained state or lets unknown values reach always-on logic.

Technical Explanation

• Stop clocks first: registers must be quiet before SAVE, or a clock edge can change state while it is being copied.
• Isolate before save and power-off: outputs are clamped before any can glitch or float, so always-on logic never sees X.
• SAVE with power still on: the shadow latch copies the register while the primary rail is stable.
• Switch off, wait for ack: the switch acknowledge is the only proof the rail actually moved; the controller waits on it in both directions.
• Wake: switch on and wait for ack, RESTORE, release isolation, then start clocks.
• Swaps that break: RESTORE before ack loads garbage, releasing isolation before RESTORE exposes reset values, and clocks before RESTORE overwrite retained state.
• Legacy form (still accepted by ICC2/PT): set_isolation_control (UPF) and set_retention_control (UPF) carry the same signals outside the strategies.

# Conceptual (not a tool command)
clk_en_cop = 0
ise = 1
cop_save = 1
cop_save = 0
pse = 0
wait pse_ack == 0
pse = 1
wait pse_ack == 1
cop_restore = 1
cop_restore = 0
ise = 0
clk_en_cop = 1
# [UPF]  mychip.upf
set_isolation ISO_COP -domain PD_COP -applies_to outputs -clamp_value 0 -isolation_supply SS_AON -isolation_signal ise -isolation_sense high
set_retention RET_COP -domain PD_COP -retention_supply SS_AON -save_signal {cop_save high} -restore_signal {cop_restore high}
create_power_switch SW_COP -domain PD_COP -input_supply_port {SWIN VDD1p0} -output_supply_port {SWOUT VDD1p0_SW} -control_port {CTRL pse} -ack_port {ACK pse_ack} -on_state {ON SWIN {CTRL}}

What To Check

• Every control signal (clk_en_cop, ise, cop_save, cop_restore, pse) comes from always-on logic in PD_MYCHIP.
• Isolation rises before SAVE and before pse falls, and falls only after RESTORE.
• The controller waits on pse_ack, not a fixed delay, in both directions.
• Clocks restart only after isolation is released.

Healthy, Suspicious & Hard-stop Results

• Healthy (illustrative): Power-aware simulation of 100 sleep and wake cycles shows no X on PD_MYCHIP inputs and every retained flop correct.
• Suspicious (illustrative): The order is right, but on wake the controller uses a fixed 500 ns delay instead of pse_ack.
• Hard stop: ise falls before cop_restore, or check_lp reports ISO_CONTROL_CONN on ISO_COP.

What The Interviewer Is Testing

• Can you give the full order and say what breaks for each swapped pair?
• Do you know why the acknowledge, not a timer, gates RESTORE?

Follow-up Question & Model Response

"Why wait for the acknowledge instead of a fixed delay?"

Candidate Model Response: Ramp time depends on process, voltage, temperature and the length of the switch chain, so any fixed delay is either wasteful or sometimes too short. The acknowledge comes from the end of the chain, so it changes only after the last switch has turned. Waiting on it ties RESTORE to the real rail instead of a guess. Many controllers still add a small fixed margin after the acknowledge.