How is well (body) biasing implemented in ICC2?

Short Answer

Well biasing drives the n-wells and p-wells from dedicated supplies instead of the rails, which shifts transistor threshold voltage: reverse bias cuts leakage and forward bias buys speed. In ICC2 you turn on the UPF-based bias mode with the enable_bias design attribute, supply sets in bias scopes then gain nwell and pwell functions that connect implicitly to bias PG pins, and check_mv_design (ICC2) enforces the bias rules.

Technical Explanation

• Purpose: a p-well slightly above ground lowers NMOS threshold for speed; slightly below ground raises it and cuts leakage. N-well bias does the same for PMOS.
• Library modeling: bias pins are PG pins with pg_type nwell or pwell, direction input or inout, and physical_connection routing_pin or device_layer.
• Enable: set_design_attributes -elements {.} -attribute enable_bias true (UPF); a block can turn it off, but can turn it on only if every parent has it on.
• Bias supplies: in a bias scope, create_supply_set (UPF) and implicit domain supply sets get power, ground, nwell and pwell functions.
• Rules checked: bias supply more on than its primary, one bias supply per domain except macros, no power pin sharing a supply with a p-well pin, no negative n-well voltage.
• Nonbias blocks: mv.upf.allow_non_bias_domain_in_bias_scope (ICC2) lets bias and nonbias domains share a scope; otherwise a nonbias block needs its own domain supply set.
• N-well-only libraries: mv.upf.enable_nwell_only_support (ICC2) handles cells with only n-well pins, and p-well checks are skipped where no pin connects.

# [UPF]  mychip.upf
set_design_attributes -elements {.} -attribute enable_bias true
create_supply_set SS_CORE
create_power_domain PD_CORE -include_scope -supply {primary SS_CORE}
set_design_attributes -elements {u_pll} -attribute enable_bias false
# [ICC2]  icc2_shell
check_mv_design
report_supply_sets

What To Check

• Every standard cell in a bias domain has bias PG pins; only macros and pads may lack them.
• Bias supplies are on whenever their primary supply is on.
• One physical_connection style (routing_pin or device_layer) per domain.
• Bias voltages per mode are set on the nwell and pwell functions, with no negative n-well value.

Healthy, Suspicious & Hard-stop Results

• Healthy (illustrative): check_mv_design reports no bias warnings and every domain uses one n-well and one p-well supply.
• Suspicious (illustrative): Six MV-083 warnings for nonbias cells that belong on a set_non_bias_approved_list.
• Hard stop: A negative voltage on an n-well supply, or a power pin and a p-well pin tied to the same supply.

What The Interviewer Is Testing

• Can you explain how well bias trades leakage against speed?
• Do you know how ICC2 models bias supplies and which rules it checks?

Follow-up Question & Model Response

"Why can a block turn biasing off inside a biased design but not on inside an unbiased one?"

Candidate Model Response: Bias supplies are created in the scope of a bias block and are available to everything below it. Turning bias off in a child just means that child ignores the bias functions. Turning it on in a child whose parent is unbiased would need bias supplies that nothing above defines. The ICC2 MV UG states the rule directly: to enable bias for a block, it must be enabled for every parent up to the top.