IntermediateQuestion 32 of 60Source: Synopsys IC Compiler II Tool Commands: connect_power_switch; Synopsys IC Compiler II Multivoltage User Guide: Multiple Power Domains in a Single Voltage Area

How are power-switch cells daisy-chained, and why?

From PDVerse Low-Power Physical Design Mentor Guide · pdVerse Mentor Guide

Short Answer

In a daisy chain, the switch enable enters the first switch cell, and each cell passes a buffered copy to the next, so the switches turn on one after another instead of all at once. That spreads the in-rush current that charges the virtual rail over time and keeps the peak within what the grid can deliver. The output of the last cell comes back as the acknowledge, telling the power controller that every switch is on.

Technical Reference DiagramHow are power-switch cells daisy-chained, and why?
A row of eight numbered header switch cells in the PD_COP voltage area: the enable U_PC/PSE enters cell 1, each cell's buffered enable output drives the next cell's enable input, and the last cell's output returns as the acknowledge PSE_ACK to the power controller, with a small VVDD ramp showing the rail rising in steps as cells turn on in order.

Technical Explanation

  • Chain: each switch cell has an enable input and a buffered enable output; output feeds the next cell's input.
  • Why: turning all switches on at once draws a huge in-rush spike that droops the always-on supply and can upset neighbours.
  • Acknowledge: the last cell's output is the ack; the controller waits for it before releasing isolation.
  • Chain length sets wake time: more cells or slower buffers mean a gentler ramp but a longer wake-up.
  • connect_power_switch -mode daisy (ICC2) connects placed switch cells; connect_power_switch -ack_out -ack_port_name (ICC2) also routes the ack.
  • Order is sorted from placement unless you use connect_power_switch -object_list -keep_order (ICC2); -direction and -start_point guide the inferred order.
  • A broken link leaves later cells off and the ack never rises, so the domain hangs in wake-up.
# [ICC2]  icc2_shell
connect_power_switch -source U_PC/PSE -port_name pse_va_cop -mode daisy -direction horizontal -start_point lower_left -ack_out U_PC/PSE_ACK -ack_port_name pse_ack_va_cop -voltage_area PD_COP
check_mv_design -power_switch

What To Check

  • Every switch cell in the voltage area is on the chain, with no floating enable inputs.
  • The ack comes from the last cell in the chain, not from an intermediate one.
  • The chain order matches the placement so neighbouring cells turn on in sequence without long routes.
  • Wake-up time from enable to ack meets the power-controller budget.

Command Checks & Actions

ICC2 (icc2_shell)connect_power_switch -source U_PC/PSE -port_name pse_va_cop -mode daisy -voltage_area PD_COP

Chains the enable through every switch cell in the voltage area.

ICC2 (icc2_shell)connect_power_switch -source U_PC/PSE -port_name pse_va_cop -mode daisy -ack_out U_PC/PSE_ACK -ack_port_name pse_ack_va_cop -object_list $sw_list -keep_order

Same chain with an explicit order and an ack routed back to the controller.

ICC2 (icc2_shell)check_mv_design -power_switch

Checks power switch strategies and switch cells after the chain is built.

Healthy, Suspicious & Hard-stop Results

  • Healthy (illustrative): All 60 PD_COP switch cells are chained, check_mv_design -power_switch (ICC2) is clean, and wake time is 1.8 us against a 2 us budget.
  • Suspicious (illustrative): Chain is complete but wake time is 1.95 us, leaving little margin if the enable buffers slow at the low-voltage corner.
  • Hard stop: One cell's enable input is unconnected, so the chain stops there and PSE_ACK never rises.

Common Mistake

The Trap: Taking the ack from the first switch cell because it is closest to the power controller.

  • The controller then sees the domain as on while most switches are still off and the virtual rail is low.
  • It releases isolation and restores state onto a half-powered domain, corrupting the restored registers.

What The Interviewer Is Testing

  • Links the daisy chain to in-rush current limiting, not just to wiring convenience.
  • Knows the ack must come from the end of the chain.
  • Knows how ICC2 orders and connects the chain.

Follow-up Question & Model Response

"How does a mother-daughter switch scheme relate to the daisy chain?"

Candidate Model Response: It adds a second stage. A first set of small, weak switches turns on through one chain and charge the virtual rail slowly with limited current. When the rail is close to VDD, a second chain turns on the large switches that carry the full load current. The two chains keep the in-rush peak low while still giving a low-resistance path once the domain is running.

Practical Example

Design Scenario: (illustrative) PD_COP has 60 header cells in 5 columns, each cell adding 30 ns of enable delay. A single daisy chain gives 60 x 30 ns = 1.8 us from U_PC/PSE to PSE_ACK, within a 2 us wake budget. Peak in-rush is 45 mA, compared with an estimated 400 mA if all 60 switched together, which would droop VDD1p0 by 60 mV and upset the always-on PD_MYCHIP logic next door. connect_power_switch (ICC2) with -mode daisy -ack_out U_PC/PSE_ACK builds the chain, and check_mv_design -power_switch (ICC2) reports no unconnected switch pins.

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