IntermediateQuestion 31 of 60Source: Synopsys IC Compiler II Multivoltage User Guide: Multiple Power Domains in a Single Voltage Area; power-gating implementation concepts

Should you implement power switches as an array or a ring?

From PDVerse Low-Power Physical Design Mentor Guide · pdVerse Mentor Guide

By Tabish Iqbal · 9+ Years VLSI Physical Design Experience

Short Answer

An array spreads switch cells in columns or a grid through the voltage area, so every standard cell is close to a switch and IR drop stays low. A ring places the switches along the voltage-area boundary, which keeps the core rows free but makes the centre the farthest point from any switch. Arrays suit large or high-current domains; rings suit small domains and hard macros that cannot take switch cells inside.

The same hatched 200 x 150 um PD_COP voltage area drawn twice: left with five evenly spaced columns of header switch cells across the area (array), right with switch cells lining the boundary (ring), each with its worst IR-drop spot marked: 48 mV at the centre of the ring in red (over the 30 mV budget) and 18 mV between columns of the array in blue (within budget). — Technical Reference DiagramShould you implement power switches as an array or a ring?

Technical Explanation

Array (grid or columns): switch cells sit inside the voltage area at a regular pitch, each feeding a nearby patch of the virtual rail.
Ring: switch cells line the voltage-area edge; current reaches the centre through the virtual rail mesh alone.
IR drop grows with distance from the nearest switch, so a ring's worst spot is the centre, and it grows with domain size.
Arrays cost placement sites inside the domain and break up rows; rings cost area at the boundary and need a strong virtual mesh.
In ICC2 the jobs are named create_power_switch_array (ICC2) and create_power_switch_ring (ICC2); check your release for their options.
connect_power_switch (ICC2) chains either style, and its -ring_direction option works with ring switches in daisy mode.
Picking a ring for a large, high-current domain leaves the centre starved during a burst, causing timing failures at low voltage.

Common Mistake

The Trap: Choosing a ring for a large domain because it keeps the floorplan clean.

The centre of the domain sits far from every switch, so the virtual rail sags there under peak current.
Timing in the middle of the block fails at the low-voltage corner, and the fix late in the flow is adding switches inside anyway, which means reopening placement in a block that was already closed.

Follow-up Question & Model Response

"Can you mix both styles?"

Candidate Model Response: Yes. Some teams put a ring around a block with a few inner columns where the current is highest, such as near a busy datapath. The ring handles the edges and the columns cover the hot spot, and you then chain all of them in one daisy chain, so the wake-up order and in-rush limit still hold. The rail analysis decides how many inner columns you actually need. Run it at the peak-current mode, not the average one, because the ring weakness only shows under a burst.

Practical Example

Design Scenario: (illustrative) PD_COP is 200 x 150 um and draws 120 mA at peak. A ring of 60 header cells along the edge gives a simulated worst drop of 48 mV at the centre, against a 30 mV budget. An array of 5 columns with 12 cells each, the same 60 cells, puts every cell within 20 um of a column and gives a worst drop of 18 mV, between columns. The team keeps the array and loses about 3% of placement sites to the switch columns. A small 40 x 40 um accelerator block elsewhere on the die uses a ring, because its worst drop is only 9 mV and its rows stay unbroken.

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