What are PVT mismatches on multivoltage cells, and how do you fix them?

Short Answer

A PVT mismatch means a cell is linked to a library pane whose process, voltage or temperature does not match the operating condition of the supplies it sits on, such as a level shifter characterized at 1.0 V in and out sitting on a 0.9 V input rail. ICC2 picks power management cells by the rule in opt.common.pvt_setting (ICC2); report_pvt (ICC2) marks which of P, V or T is off, and fix_mv_design -verbose (ICC2) reports PVT violations on buffers, inverters, tie cells and diodes.

Technical Explanation

• Default rule: voltage_range_match, where each supply's set_voltage (ICC2) value must fall inside the library cell's minimum and maximum voltage for each corner.
• Stricter modes: exact_match needs process label, process number, rail voltage and temperature to match; range_match checks voltage and temperature ranges.
• closest_match order: all PVT exact, process label, process number, voltage exact, voltage range, temperature exact, temperature range, then all mismatched.
• Per cell type: append =ls, =iso, =els, =ret or =buf; opt.common.pvt_setting (ICC2) overrides the older allow_incorrect_pvt and prefer_exact_pvt options.
• Tolerating it: opt.common.allow_incorrect_pvt (ICC2), default none, lets optimization use multivoltage library cells with incorrect PVT.
• What breaks: delay, power and switching thresholds for that cell come from the wrong operating point, so signoff numbers no longer describe silicon.

# [ICC2]  icc2_shell
report_pvt
set_app_options -name opt.common.pvt_setting -value "exact_match=ls, range_match=iso"
analyze_mv_feasibility -level_shifter -format html
fix_mv_design -verbose

What To Check

• report_pvt per corner: no mismatch mark on P, V or T for any library used by multivoltage cells.
• Each supply's set_voltage value per corner matches the pane its cells link to.
• Level shifters link to panes characterized for both their input and output rails.
• Any allow_incorrect_pvt setting is documented and removed before signoff.

Healthy, Suspicious & Hard-stop Results

• Healthy (illustrative): report_pvt shows no mismatch marks at either corner, and fix_mv_design -verbose reports no PVT violations.
• Suspicious (illustrative): report_pvt marks only the process number (1.1 set, 1 effective) on one library while V and T match.
• Hard stop: Level shifters in PD_CPU link to a 1.0 V-only pane while VDD0p9 is set to 0.9 V at every corner.

What The Interviewer Is Testing

• Do you know how ICC2 matches operating conditions and in which order it falls back?
• Can you tell when tolerating a mismatch is acceptable and when it is not?

Follow-up Question & Model Response

"When is it acceptable to allow a PVT mismatch?"

Candidate Model Response: Early in the flow, when the final libraries are not released and you only need placement and rough timing to keep moving. It can also be tolerated for a cell whose behaviour barely depends on the mismatched parameter, if the library owner agrees in writing. It is never acceptable at timing or power signoff, because every number from that cell comes from the wrong operating point. Keep the setting in one clearly named script so it cannot leak into the signoff run.