How do you sign off timing for a DVFS design in PrimeTime?

Short Answer

You can run one scenario per voltage combination, but the count grows as levels to the power of domains and it is easy to skip a mixed pair. Simultaneous multivoltage analysis (SMVA) in PrimeTime times every path under every legal combination of its domains' levels in one run, which catches the cross-domain path that fails only when one side is fast and the other slow.

Technical Explanation

• Scenario approach: each level combination is a separate PT scenario; two domains with two levels already need four per PVT corner.
• Mixed pairs matter: on a cross-domain path, launch and capture clocks scale with different supplies, so skew shifts and hold can fail in only one mixed pair.
• SMVA: with timing_enable_cross_voltage_domain_analysis (PT) true, graph-based analysis covers all supply combinations for each path, excluding impossible ones, in one run.
• Named levels: set_voltage_levels (PT) names references such as lo and hi on a supply group; set_voltage (PT) with -reference_name sets each value.
• Requirements: UPF power intent, scaling library groups, CCS noise data in every library, and PrimeTime-ADV-PLUS licenses.
• Reporting: each voltage configuration is its own path, report_timing (PT) prints a Voltage Config line, and -domain_crossing only_crossing keeps cross-domain paths.
• What breaks: timing only all-low and all-high misses the mixed pair, and hold fails in silicon when software runs one domain fast and the other slow.

# [PrimeTime]  pt_shell
set_app_var timing_enable_cross_voltage_domain_analysis true
set sg_gpu [get_supply_groups VDD_GPU]
set_voltage_levels -reference_names {lo hi} $sg_gpu
set_voltage -reference_name hi -object_list $sg_gpu 0.95
set_voltage -reference_name lo -object_list $sg_gpu 0.75
set sg_dsp [get_supply_groups VDD_DSP]
set_voltage_levels -reference_names {lo hi} $sg_dsp
set_voltage -reference_name hi -object_list $sg_dsp 1.10
set_voltage -reference_name lo -object_list $sg_dsp 0.90
check_timing -include supply_net_voltage
report_timing -domain_crossing only_crossing

What To Check

• Every DVFS supply group has named levels and a value for each level.
• check_timing reports no unconnected PG pins and no supply without a voltage.
• Cross-domain paths appear under every legal voltage configuration, not only uniform ones.
• Level shifters on crossings are characterized for both their input and output rails.

Healthy, Suspicious & Hard-stop Results

• Healthy (illustrative): Worst cross-domain hold slack is +12 ps across all four GPU and DSP configurations.
• Suspicious (illustrative): Only the GPU:hi, DSP:lo configuration sits within 5 ps of zero; review its margin before closing.
• Hard stop: A GPU-to-DSP path fails hold at -18 ps in GPU:hi, DSP:lo while the all-high and all-low runs both pass.

What The Interviewer Is Testing

• Do you see why mixed voltage pairs on cross-domain paths are the risk, not the uniform corners?
• Can you set up named voltage references and read the Voltage Config in a report?

Follow-up Question & Model Response

"If SMVA exists, why do some teams still run one scenario per DVFS mode?"

Candidate Model Response: SMVA needs PrimeTime-ADV-PLUS licenses, scaling library groups and CCS noise data, and not every flow has all three. Per-mode scenarios also match how the chip was characterized and how ECO work is split across people. The cost is coverage, because you must enumerate every legal mixed pair by hand. If you go that way, generate the scenario list from the power-state table rather than a spreadsheet.