What is the difference between fine-grain and coarse-grain clock gating, and what does an integrated clock gating (ICG) cell do that a plain AND gate cannot?
From PDVerse Low-Power Physical Design Mentor Guide · pdVerse Mentor Guide
Definition
Fine-grain clock gating disables the clock to individual registers or small groups of registers based on a local, register-specific enable condition, while coarse-grain clock gating disables the clock to an entire functional block or clock-tree branch at once based on a block-level enable condition; an integrated clock gating (ICG) cell is the specific, glitch-safe library cell used to implement either, in place of a naive AND gate directly on the clock signal.
Mentor Explanation
Fine-grain gating targets the many individual registers in a design whose existing enable signal (e.g., an existing if (load_enable) reg <= data; RTL pattern) can be automatically recognized by synthesis and converted from "clock always toggles, enable gates the data" into "enable gates the clock itself" — saving the register's own clock-toggle power specifically on cycles it wasn't going to update anyway, with fine granularity (potentially different registers gated independently). Coarse-grain gating instead disables an entire branch of the clock tree — an entire idle functional unit or block — based on one shared enable, saving not just register power but also the clock buffer/tree power for that whole subtree, at the cost of being all-or-nothing for everything under that branch. The key implementation detail for both: you can't just AND a raw enable signal with the clock directly, because if the enable signal changes anywhere except when the clock is already low, it can produce a runt pulse or a glitch on the gated clock output — an ICG cell solves this by internally latching the enable signal with a level-sensitive latch clocked by the (ungated) clock, guaranteeing the enable can only take effect while the clock is already low, so the gated output is always a clean, full clock pulse or nothing.
Example
A synthesis tool automatically inferring clock gating from RTL like if (enable) q <= d; will insert individual (fine-grain) ICG cells per register group with a shared enable condition, while a design might separately implement one coarse-grain ICG cell at the root of an entire idle coprocessor's clock branch, controlled by a "coprocessor active" signal, to save the whole subtree's clock-tree power whenever that coprocessor isn't in use at all.
Why It Matters
Clock gating (in either granularity) is typically the single largest dynamic-power-saving technique available at the RTL/synthesis level, because clock trees toggle every cycle regardless of whether useful work is happening, and registers plus their local clock buffers are often the single largest contributor to total switching activity in a design. Using a plain AND gate instead of a proper ICG cell isn't just non-optimal, it's a functional bug risk — glitches on a clock line can cause double-clocking or missed edges that gate-level simulation with ideal clock waveforms won't necessarily catch, making this exactly the kind of detail that separates "I know clock gating saves power" from "I know why it has to be implemented with a specific cell type."
Command
# Conceptual ICG cell behavior (standard-cell library element, not a UPF/RTL keyword):
# CGC: enable_latched = (clk == 0) ? enable : enable_latched; // latch enable only while clk low
# gated_clk = clk AND enable_latched; // glitch-free gated clockCommon Beginner Mistake
Implementing clock gating in RTL as a direct AND of the enable signal with the raw clock (assign gated_clk = clk & enable;) instead of relying on synthesis to infer a proper ICG cell (or instantiating one explicitly). A raw AND gate has no protection against the enable signal changing while the clock is high, which can produce a glitch or runt pulse on the gated clock — a real functional hazard, not just a style preference.
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