ExpertQuestion 25 of 50Source: Synopsys IC Compiler II Implementation User Guide: Setting Up Multivoltage Designs and Voltage Driven Power Switch Cell Sizing; Synopsys IC Compiler II Multivoltage User Guide: Multiple Power Domains in a Single Voltage Area

How do you floorplan a switchable voltage area so IR drop and wake-up both work?

From PDVerse Low-Power Physical Design Mentor Guide · pdVerse Mentor Guide

By Tabish Iqbal · 9+ Years VLSI Physical Design Experience

Short Answer

Put the voltage area close to its supply bumps, spread the switches evenly under the always-on straps so every region of the block has a short path to one, and reserve an always-on channel for the cells that must stay alive. Then check static and dynamic IR on both the real and switched rails, and ramp-up current for the chosen enable order. Switch count sets IR drop; switch enable order sets wake-up time and in-rush.

Floorplan of the PD_GPU voltage area with a guard band, 12 switch columns under vertical VDD0p9 straps, a horizontal always-on channel for AO buffers and isolation cells, the supply bumps on the near edge, and a ledger: 240 switches, 22 mV target, 2.5 percent area. — Technical Reference DiagramHow do you floorplan a switchable voltage area so IR drop and wake-up both work?

Technical Explanation

Location: place the VA near the bumps or pads that feed it; every millivolt lost on the AON grid before the switch comes out of the budget.
Switch pattern: columns or a grid at a fixed pitch, aligned to upper-layer AON straps, so each switch reaches a strap through a short via stack.
Density: the switch count comes from the IR target; a denser pattern cuts IR and raises area, switch leakage and in-rush.
AO channel: keep rows or a channel for AO buffers, isolation cells and retention control, with secondary PG straps they can reach.
Guard band: create_voltage_area -guard_band (ICC2) keeps cells of other VAs out, so power planning does not short the two rails.
Chain entry: start the daisy chain near the controller and supply entry, so the first switches charge the rail where the grid is strongest.

# [ICC2]  icc2_shell
create_voltage_area -name VA_GPU -power_domains {PD_GPU} -region {{0 0} {1200 800}} -guard_band {{5 5}}
connect_power_switch -source U_PC/gpu_sleep -port_name gpu_sleep -mode daisy -direction horizontal -start_point lower_left -voltage_area VA_GPU
analyze_rail -voltage_drop static -nets {VDD0p9 VDD_GPU_SW VSS}
analyze_rail -voltage_drop dynamic -nets {VDD0p9 VDD_GPU_SW VSS}
check_mv_design

What To Check

Worst static and dynamic drop on VDD_GPU_SW sits inside the budget in every corner of the VA.
No switch is more than one strap pitch from an AON strap.
AO cells have secondary PG within reach.
Guard band and VA shape leave no sliver the placer cannot use.

Command Checks & Actions

ICC2 (icc2_shell)create_voltage_area -name VA_GPU -power_domains {PD_GPU} -region {{0 0} {1200 800}} -guard_band {{5 5}}

Create the VA with a keep-out band

ICC2 (icc2_shell)connect_power_switch -source U_PC/gpu_sleep -port_name gpu_sleep -mode daisy -voltage_area VA_GPU

Chain the switch enables inside the VA

ICC2 (icc2_shell)analyze_rail -voltage_drop static -nets {VDD0p9 VDD_GPU_SW VSS}

Check static drop on the real and switched rails

ICC2 (icc2_shell)analyze_rail -voltage_drop dynamic -nets {VDD0p9 VDD_GPU_SW VSS}

Check dynamic drop during switching

ICC2 (icc2_shell)check_mv_design

Confirm power intent and PG connectivity after the floorplan

Healthy, Suspicious & Hard-stop Results

Healthy (illustrative): Worst drop on VDD_GPU_SW is 19 mV against a 22 mV target, spread evenly across the VA.
Suspicious (illustrative): Average drop is 15 mV, but the corner far from the bumps shows 24 mV.
Hard stop: Drop exceeds 22 mV over a large region, or AO cells sit with no secondary strap in reach.

Common Mistake

The Trap: Packing all switches along one edge of the VA to keep the core clean.

Current then crosses the whole block on the switched rail, so the far side droops even though the switch count meets the budget.

What The Interviewer Is Testing

Do you plan the VA around supply entry, not just the logic shape?
Can you separate the IR problem from the wake-up problem?

Follow-up Question & Model Response

"The IR target is met but wake-up is now too slow. What do you change first?"

Candidate Model Response: Leave the switch count alone, since it is set by IR. Change the enable topology instead: split the daisy chain into parallel branches, or use a fishbone so branches enable together. Each change raises the in-rush peak, so re-run ramp-up analysis and check the AON neighbours. Only if that fails do you revisit the VA location or the grid.

Practical Example

Design Scenario: (illustrative) PD_GPU runs at 0.9 V with a 400 mA peak and a 22 mV switch budget. The team places 240 switches (illustrative HEADER_X8, 7.5 ohm each, so 12.5 mV across the bank) in 12 columns at 100 um pitch under the VDD0p9 straps, about 2.5 percent of a 1.2 mm by 0.8 mm VA. The first run shows 24 mV at the corner far from the bumps; moving the VA 300 um toward the bump field brings the worst drop to 19 mV.

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