What library cell attributes does a low-power cell need to have (e.g. is_isolation_cell, is_level_shifter, switch_cell_type)?
From PDVerse Low-Power Physical Design Mentor Guide · pdVerse Mentor Guide
Explanation
For the tool to recognize and correctly use a low-power cell -isolation, level shifter, retention, clock gate, or always-on -- the Liberty library must mark it with specific cell- and pin-level attributes. Without these, the cell is treated as an ordinary logic cell and cannot be automatically selected for power-management insertion.
Implementation Walkthrough
Isolation cells need is_isolation_cell = true plus isolation_cell_enable_pin set on the enable pin. Level shifters need is_level_shifter = true; enable-type shifters additionally need level_shifter_enable_pin on the enable pin. Retention cells use the cell-level attribute retention_cell (e.g. retention_cell : DRFF;) plus pin-level retention_pin identifying a pin as save, restore, or save_restore, along with related_power_pin, related_ground_pin, always_on : true on the SAVE/RESTORE pins, and power_down_function on the data output. Clock-gate cells use clock_gating_integrated_cell (with values like 'latch_posedge_precontrol' or 'non_posedge') plus pin attributes clock_gate_clock_pin, clock_gate_enable_pin, clock_gate_out_pin, and clock_gate_test_pin. Any standard cell participating in a multivoltage design should be 'pg-pin ready,' using pg_pin groups with voltage_name and pg_type (primary_power/primary_ground/backup_power/ PD_TOP PD_A (subdomain) PD_B (subdomain) create_composite_domain -subdomains {PD_A PD_B} backup_ground/internal_power/internal_ground), plus related_power_pin/related_ground_pin/power_down_function/ related_pg_pin at the pin level. Always-on cells are marked with an always_on attribute.
Switch-by-switch
is_isolation_cell (bool): flags a cell as usable for isolation
insertion; isolation_cell_enable_pin: names the enable pin;
is_level_shifter (bool): flags a cell as a level shifter;
level_shifter_enable_pin: enable pin for enable-type shifters;
retention_cell (string, e.g. DRFF): flags/type-names a retention
cell; retention_pin (save|restore|save_restore, value): identifies a
pin's retention role; always_on (bool, pin-level): marks a pin that
must stay powered through shutdown; clock_gating_integrated_cell
(string values): flags an ICG cell and its latch topology; pg_pin ->
voltage_name / pg_type: defines each physical power/ground pin's
electrical role.Expected Tool Behavior
With these attributes correctly present, create_mv_cells, map_isolation_cell, map_level_shifter_cell, map_power_switch, and map_retention_cell can automatically select and connect the right physical cells for each UPF strategy; missing attributes force the tool to fall back to generic GTECH cells or fail to map at all.
Example
The DRFFQX0 retention flip-flop: pg_pin(VDD){pg_type: primary_power;}, pg_pin(VDDG){pg_type: backup_power;}, retention_cell : DRFF;, pin(NRESTORE){retention_pin(restore,"1"); always_on: true;}, pin(SAVE){retention_pin(save,"0"); always_on: true;}, pin(Q){power_down_function: "!VDD + !VDDG + VSS";}.
Common Mistake
Relying entirely on the tool's automatic pin-name-based inference (mv.cells.infer_complex_retention_cells) instead of setting explicit Liberty attributes, then being surprised when a nonstandard retention cell isn't recognized.
Likely Error Or Warning
A warning is issued when mv.cells.infer_complex_retention_cells cannot find a matching retention lib cell via pin-name matching; separately, map_retention_clamp_cell is NOT a valid UPF command and errors at load_upf if present in a UPF file, even though it resembles the legitimate mapping commands.
Debugging Approach
Check the library source for is_isolation_cell / is_level_shifter / retention_cell / clock_gating_integrated_cell / always_on attributes on the candidate cells; if automatic inference fails, define the user attribute retention_equivalent (via define_user_attribute + set_attribute) to manually associate the cell.
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