What are two-pin, single-pin and zero-pin retention registers?

Short Answer

They differ in how many retention control pins they have. A two-pin register has separate SAVE and RESTORE pins, a single-pin register uses one save_restore pin whose level selects the mode, and a zero-pin register has no control pin because its subordinate latch sits on an always-on supply. Zero-pin registers only retain if the clock and asynchronous pins are held inactive, so ICC2 inserts clamp cells that you must check.

Technical Explanation

• Two-pin: a balloon latch on the retention supply with separate SAVE and RESTORE, so the controller times save before power-off and restore after power-up.
• Single-pin: one save_restore pin whose voltage level selects save or restore mode, saving one control net per register.
• Zero-pin: the subordinate latch is always on and holds data through shutdown; 1801-2015 uses -retention_condition instead of save and restore signals.
• Clock clamp: retention needs the clock held inactive, low for a rising-edge register, so ICC2 inserts isolation clamp cells on clock and async set/reset paths.
• Mapping: map_retention_cell (UPF) picks register cells; map_retention_clamp_cell (ICC2) picks clamp cells and is not a UPF command.
• Legacy form (still accepted by ICC2/PT): -retention_power_net/-retention_ground_net instead of -retention_supply, with SAVE and RESTORE on set_retention_control (UPF).
• What breaks: a clamp with the wrong value or on a switched supply lets the clock toggle during shutdown and corrupts the held state.

# [UPF]  design.upf
set_retention RET_COP -domain PD_COP -retention_supply SS_AON -save_signal {U_PC/save high} -restore_signal {U_PC/restore high}
map_retention_cell RET_COP -domain PD_COP -lib_cells {RETFF_2P_X1}
# [ICC2]  icc2_shell
# RET_ZP is a zero-pin strategy on PD_COP, loaded with the UPF
map_retention_clamp_cell RET_ZP -domain PD_COP -clock_clamp_lib_cells {ISO_NOR_X1} -async_clamp_lib_cells {ISO_NOR_X1}
report_mv_cells -retention
report_mv_cells -retention_clamp -verbose
check_mv_design

What To Check

• Two-pin cells get both SAVE and RESTORE nets from the power controller.
• Zero-pin clamp values match the inactive clock level: 0 for rising-edge registers.
• Clamp cells on clock and async paths sit on an always-on supply.
• Every zero-pin register group has a clamp in report_mv_cells -retention_clamp -verbose (ICC2).

Healthy, Suspicious & Hard-stop Results

• Healthy (illustrative): 1,200 PD_COP registers map to RETFF_2P_X1, and 300 zero-pin registers show clamps holding 0 on SS_AON.
• Suspicious (illustrative): Clamps use dual-rail isolation cells: allowed, but confirm each one takes its supply from the always-on rail.
• Hard stop: Clamps remain GTECH isolation cells because no listed library cell was suitable: the clock clamp does not exist in silicon.

What The Interviewer Is Testing

• Can you say which control nets each retention type needs from the power controller?
• Do you know why zero-pin retention needs a clock clamp?

Follow-up Question & Model Response

"Why would you pick zero-pin retention despite the clamp overhead?"

Candidate Model Response: It needs no save or restore nets, so the power controller and the routing get simpler and there is no save or restore timing to verify. The price is an always-on latch in every register, which leaks during shutdown, plus clamp cells and always-on buffering on clock and async nets. It suits blocks with modest register counts where control wiring is the pain. For large register counts, the leakage of all those always-on latches can outweigh the savings.