What is output load, and why does it affect delay?
From PDVerse MMMC Interview Masterclass · pdVerse Mentor Series
Direct answer
Output load is the total capacitance a driving cell has to charge or discharge on its output — the receiving pin's own input capacitance plus whatever the connecting wire adds. A heavier load takes longer to charge, so the driver's delay goes up.
Mentor explanation
A logic gate isn't just flipping a value — physically, it's pushing or pulling current into a capacitor formed by everything downstream of it. If that capacitor is small, it charges quickly and the gate looks fast. If it's large — a big receiving gate, a long wire, high fanout — the same driver looks noticeably slower, even though nothing about the driver itself changed. This is exactly why the library characterizes delay across a range of output loads: the driver's "speed" is never a fixed number by itself.
Example or conceptual chain
Driver -> pin capacitance + interconnect capacitance (C_LOAD). A heavier load takes longer to charge.
Key takeaways
- Output load is the total capacitance a driving cell has to charge or discharge on its output — the receiving pin's own input capacitance plus whatever the connecting wire adds.
- A heavier load takes longer to charge, so the driver's delay goes up.
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