What are parasitics, in plain language?
From PDVerse MMMC Interview Masterclass · pdVerse Mentor Series
Direct answer
Parasitics are the unavoidable electrical side effects of a physical wire — resistance along its length, capacitance to the ground plane and other reference layers, and coupling capacitance to neighboring wires. None of this is intentional; it's just what happens when you route metal on a chip.
Mentor explanation
When we draw a wire in a schematic, we usually treat it as a perfect, instant connection. Physically, that wire is a strip of metal with real resistance, and it sits close to other metal (both a ground reference and neighboring signal wires), so it forms real capacitors. None of this was "designed in" on purpose — it's a side effect of the interconnect existing in physical space at all. STA has to account for these effects because they directly change how a signal's edge looks by the time it reaches the receiver.
Example or conceptual chain
A routed net contributes resistance, capacitance to reference layers, and coupling capacitance to neighboring aggressors.
Key takeaways
- Parasitics are the unavoidable electrical side effects of a physical wire — resistance along its length, capacitance to the ground plane and other reference layers, and coupling capacitance to neighboring wires.
- None of this is intentional; it's just what happens when you route metal on a chip.
Self-check: can you answer this aloud?
Try a 45-second answer using this structure:
- State the direct answer.
- Explain the timing or physical reason.
- Name one caveat.
- Say how you would verify it in a real flow.
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