Level 1 · Foundations

Beginner MMMC Interview Questions

Build a precise vocabulary for modes, corners, libraries, parasitics, delay corners, analysis views, setup, and hold.

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What to practise at this level

Aim to explain each building block without mixing behavioral intent with physical conditions. Your answer should stay simple while still naming the caveat that makes it signoff-safe.

  1. 01 What is MMMC, and why can't one timing run tell the whole story?Beginner · MMMC stands for Multi-Mode Multi-Corner analysis — running timing across every operating mode and physical condition the chip must survive, instead of just one. We need it because a single netlist has to work correctly under many different combinations of behavior and environment, and no single run can represent all of them at once.
  2. 02 What is a "mode," in plain terms?Beginner · A mode describes what the chip is doing right now — running its real function, shifting scan data during test, capturing a test response, or sitting in a low-power state. The netlist doesn't change between modes, but which clocks, which logic paths, and which constraints are actually valid does change.
  3. 03 What's the actual difference between a "mode" and a "corner"?Beginner · A mode answers "what is the chip doing?" A corner answers "under what physical or electrical condition is it doing it?" They are two completely separate questions, and a real analysis view always answers both.
  4. 04 What is a constraint mode?Beginner · A constraint mode is the bundle of timing intent — clocks, generated clocks, input/output delays, exceptions, case analysis, clock groupings — that applies to one specific mode. It's the SDC-level description of "what is legal and what matters" for that behavior.
  5. 05 Why can't we just use one SDC file for every operating condition?Beginner · It's not that using one file is physically impossible — you could write it. The real problem is that different modes can require genuinely different timing intent, and cramming all of it into one file makes that intent contradictory, hard to trace, and easy to get wrong.
  6. 06 What does PVT actually stand for, and what does each letter mean?Beginner · Process, Voltage, Temperature — the three physical and electrical conditions that determine how fast or slow a manufactured cell actually behaves compared to its nominal design target.
  7. 07 Why doesn't a standard cell have just one fixed delay?Beginner · Because delay isn't a stored number — it's the output of a function that depends on the PVT condition, the input transition (slew), the output load, which specific timing arc is being measured, and the model used to compute it.
  8. 08 What is a timing library, really?Beginner · A timing library (typically in Liberty format) is the characterized model of how a specific cell behaves electrically — its pins, its logic function, and tables of delay, transition, and setup/hold behavior across a range of input slews and output loads, all captured under one PVT condition.
  9. 09 What is input slew, and why does it change a cell's delay?Beginner · Slew is how fast a signal transitions between logic levels — a sharp, fast edge versus a slow, lazy one. A slower input edge makes the receiving cell switch more gradually, which increases its own delay and the sharpness of its output edge.
  10. 10 What is output load, and why does it affect delay?Beginner · Output load is the total capacitance a driving cell has to charge or discharge on its output — the receiving pin's own input capacitance plus whatever the connecting wire adds. A heavier load takes longer to charge, so the driver's delay goes up.
  11. 11 What are parasitics, in plain language?Beginner · Parasitics are the unavoidable electrical side effects of a physical wire — resistance along its length, capacitance to the ground plane and other reference layers, and coupling capacitance to neighboring wires. None of this is intentional; it's just what happens when you route metal on a chip.
  12. 12 Why isn't a routed wire just an ideal connection?Beginner · Because a real wire has distributed resistance and capacitance along its length, not one lump sum at the end. Each little segment of the wire has its own R and C, so a signal loses time and sharpness gradually as it travels, not all at once.
  13. 13 What is SPEF, and what does it actually represent?Beginner · SPEF (Standard Parasitic Exchange Format) is the file format used to hand off extracted interconnect parasitics — resistance, ground capacitance, and coupling capacitance for every net — from the extraction tool to the timing engine. It's the recorded data, not the policy for what condition it represents.
  14. 14 What is an RC corner?Beginner · An RC corner is a named, characterized interconnect condition — a set of assumptions about wire resistance and capacitance — used consistently across the flow. If the timing library describes how the cells behave, the RC corner describes how the wires between them behave.
  15. 15 What is a library set?Beginner · A library set is a named, consistent group of timing libraries — standard cells, memories, I/O, and any hard macros — that all belong to the same cell timing condition. It exists so the whole design is characterized under one coherent story, not a mismatched patchwork.
  16. 16 What is a delay corner?Beginner · A delay corner is the combination of a library set (how the cells behave) and an RC corner (how the wires behave) into one unified condition for computing delay. It answers, in one object, "how do cells and wires behave together, right now?
  17. 17 Is a delay corner the same thing as a setup view or a hold view?Beginner · No. A delay corner only describes the cell-plus-wire condition. Whether that condition is used for a setup check, a hold check, or both is decided separately, when the delay corner is paired with a constraint mode and that combination is explicitly activated.
  18. 18 What is an analysis view?Beginner · An analysis view is the complete, named timing world an STA engine actually analyzes — built by pairing one constraint mode (the timing intent) with one delay corner (the cell-plus-wire condition). It's the object where "what is the chip doing" finally meets "under what condition.
  19. 19 What is setup timing, and what is hold timing, in plain terms?Beginner · Setup checks whether data launched from one flop arrives at the next flop early enough to be captured correctly on the upcoming clock edge. Hold checks whether that same data avoids arriving so early that it gets captured on the wrong edge instead.
  20. 20 What are the major files an MMMC timing run actually needs?Beginner · At minimum: a netlist for connectivity, timing libraries for cell behavior, an SDC for timing intent, parasitic data for interconnect behavior, and an MMMC configuration that ties modes and corners together into views.