Why doesn't a standard cell have just one fixed delay?
From PDVerse MMMC Interview Masterclass · pdVerse Mentor Series
Direct answer
Because delay isn't a stored number — it's the output of a function that depends on the PVT condition, the input transition (slew), the output load, which specific timing arc is being measured, and the model used to compute it.
Mentor explanation
It's tempting to think of a library as a lookup table of "this cell equals this many picoseconds," but that's not how it works. The same physical inverter can report a very different delay depending on how fast its input is switching and how much capacitance it's driving on its output, on top of the PVT condition it was characterized under. That's why a netlist alone tells you nothing about actual delay — it tells STA which cell exists, and the library plus the surrounding context tells STA how that instance of the cell actually behaves right now.
Example or conceptual chain
Cell delay = f(PVT, input slew, output load, transition direction, timing arc, characterization model).
Key takeaways
- Because delay isn't a stored number — it's the output of a function that depends on the PVT condition, the input transition (slew), the output load, which specific timing arc is being measured, and the model used to compute it.
Self-check: can you answer this aloud?
Try a 45-second answer using this structure:
- State the direct answer.
- Explain the timing or physical reason.
- Name one caveat.
- Say how you would verify it in a real flow.
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