What is a timing library, really?
From PDVerse MMMC Interview Masterclass · pdVerse Mentor Series
Direct answer
A timing library (typically in Liberty format) is the characterized model of how a specific cell behaves electrically — its pins, its logic function, and tables of delay, transition, and setup/hold behavior across a range of input slews and output loads, all captured under one PVT condition.
Mentor explanation
The netlist tells the STA engine which cells exist and how they're wired together — it says "there is a NAND2 here, and its output connects to this net." That's connectivity, not behavior. The timing library is the piece that says how that NAND2 actually responds: how much delay from input to output, how the output transition looks, what setup and hold windows its internal flops need. Without the library, the netlist is just a wiring diagram. With it, the netlist becomes something STA can actually time.
Key takeaways
- A timing library (typically in Liberty format) is the characterized model of how a specific cell behaves electrically — its pins, its logic function, and tables of delay, transition, and setup/hold behavior across a range of input slews and output loads, all captured under one PVT condition.
Self-check: can you answer this aloud?
Try a 45-second answer using this structure:
- State the direct answer.
- Explain the timing or physical reason.
- Name one caveat.
- Say how you would verify it in a real flow.
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