BeginnerQuestion 140 of 157Source: Synopsys ICC2 Implementation User Guide: ECO

When does adding a buffer make a path faster?

From PDVerse PnR Interview Handbook · pdVerse Mentor Guide

By Tabish Iqbal · 9+ Years VLSI Physical Design Experience

Short Answer

A buffer speeds up a path when the wire it breaks is long enough that its RC delay is larger than the buffer delay added. Wire delay grows roughly with the square of length, because both resistance and capacitance grow with length. Splitting the wire into shorter segments makes total delay grow roughly linearly. On a short wire, a buffer only adds delay.

Layout view of a long unbuffered wire between two cells, then the same wire with evenly spaced repeaters, with delay annotated as growing with length squared before and roughly linearly after. — Technical Reference DiagramWhen does adding a buffer make a path faster?

Technical Explanation

A wire has resistance and capacitance per unit length. The distributed RC delay of an unbuffered wire is about half of r times c times length squared, so doubling the length makes it four times slower.
A buffer halfway along cuts one long RC into two short ones. Each segment has a quarter of the original RC delay, so the wire part drops to half, and you pay one buffer delay.
This only wins past a crossover length. Below it, the buffer delay is more than the RC delay it removes. The crossover depends on the metal layer and the buffer size.
Buffers also sharpen transitions. A slow edge at the end of a long wire slows the cell it feeds, so fixing the wire often helps the next stage too.
Buffers can isolate a critical load from a heavy non-critical one. Putting the non-critical loads behind a buffer lets the driver see less capacitance on the critical branch.
In ICC2, add_buffer_on_route (ICC2) places repeaters along an existing route using -repeater_distance and -first_distance. add_buffer (ICC2) inserts at a pin or net without following the route. PrimeTime uses insert_buffer (PT).
Setup fixing in PrimeTime uses sizing alone by default, so buffer insertion for setup is either explicit in ICC2 or enabled through the fixing methods in PT.

Formula Or Decision Rule

Unbuffered wire: Twire ≈ 0.5 · r · c · L².
Wire in k equal segments with k - 1 buffers: T ≈ 0.5 · r · c · L² / k + (k - 1) · Tbuf.
Buffering helps when the saving 0.5 · r · c · L² · (1 - 1/k) is larger than (k - 1) · Tbuf.
With optimal spacing, total delay grows roughly linearly with L.

What To Check

Wire length and the net Incr in the timing report.
The metal layer, since resistance per unit length differs by layer.
Whether the net already has repeaters and their spacing.
Transition at the far load before and after.

Command Checks & Actions

ICC2 (icc2_shell)report_timing -delay_type max

Finds the long net and its Incr on the critical path.

ICC2 (icc2_shell)add_buffer_on_route net1 -lib_cell BUF1 -repeater_distance 150 -first_distance 100

Places repeaters along the existing route, the first at 100 um and then every 150 um.

Healthy, Suspicious & Hard-stop Results

Healthy (illustrative): Net delay cut by at least half with repeaters spaced evenly and transitions under 100 ps.
Suspicious (illustrative): A buffered net that gains under 5 ps. The wire was below the crossover length, so remove the buffer.
Hard stop: Buffers inserted where there is no legal space, causing large legalization moves. Undo and pick positions with room.

Common Mistake

The Trap: Adding buffers to every net on a failing path. On short nets of 10 to 20 um, each buffer adds about 25 ps and saves 2 ps of wire delay. A path that failed by -12 ps now fails by -80 ps, and it takes another ECO loop to remove the buffers.

What The Interviewer Is Testing

Knowing why wire delay grows with the square of length.
Understanding the crossover length idea, even without exact numbers.
Using add_buffer_on_route (ICC2) versus add_buffer (ICC2) sensibly.

Follow-up Question & Model Response

"Why does buffering help more on a thin lower metal layer than on a thick upper layer?"

Candidate Model Response: Thin lower layers have much higher resistance per unit length. The r term in the RC product is larger, so the length squared penalty bites sooner and the crossover length is shorter. On a thick upper layer, a long wire has less RC delay and may not need a buffer at all. That is why long routes are often promoted to upper layers before buffering is considered.

Practical Example

Tapeout Scenario: A 2 mm net on a lower layer has an unbuffered RC delay of about 400 ps (illustrative, using 0.5 · r · c · L²). Splitting it into 4 segments with 3 buffers gives 400 / 4 = 100 ps of wire delay plus 3 × 30 ps = 90 ps of buffer delay, 190 ps total. That saves 210 ps. The same logic on a 100 um net gives 1 ps of wire delay; one buffer would add 30 ps for nothing.

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