BeginnerQuestion 138 of 157Source: Synopsys PrimeTime User Guide: ECO Flow

How does upsizing a cell fix setup, and what does it cost?

From PDVerse PnR Interview Handbook · pdVerse Mentor Guide

By Tabish Iqbal · 9+ Years VLSI Physical Design Experience

Short Answer

Upsizing replaces a cell with a stronger version of the same function, which drives its load faster and cuts delay. The cost is a larger input capacitance, which slows the stage before it, plus more area and leakage. It is the first fix PrimeTime tries for setup: by default fix_eco_timing -type setup (PT) uses cell sizing alone.

Schematic comparing an X1 and an X4 inverter in the same path, with a ledger of illustrative delay, input capacitance and leakage for each size. — Technical Reference DiagramHow does upsizing a cell fix setup, and what does it cost?

Technical Explanation

A larger drive strength means wider transistors and lower output resistance. The cell charges its load faster, so both its delay and its output transition improve, which also speeds up the next stage.
The gain is largest when the cell drives a heavy load. Upsizing a cell that drives one nearby pin saves very little, because its delay was mostly intrinsic.
Wider transistors have larger gate capacitance. The input pin of an X4 cell loads its driver more than an X1 does, so the previous stage slows down. If that stage is also weak, the net gain can be small or even negative.
Area grows with drive strength, and a larger footprint may not fit in place after routing. ICC2 legalization then has to move neighbours, which disturbs other paths.
Leakage also grows with transistor width. Sizing many cells on non-critical paths adds leakage for no timing benefit.
Sizing is the least disruptive fix because it keeps the netlist connections the same. That is why PrimeTime setup fixing uses sizing by default and why the command exists in both tools as size_cell (PT) and size_cell (ICC2).
Same command name, different context: size_cell (PT) changes the cell in the PrimeTime session so write_changes (PT) can export it, while size_cell (ICC2) changes the layout and has spare-cell awareness for freeze-silicon ECOs.

What To Check

The load the cell drives, since the gain depends on it.
Slack and transition on the stage before the sized cell.
Whether the larger footprint fits without moving neighbours.
Leakage and area change across all sized cells.

Command Checks & Actions

PrimeTime (pt_shell)size_cell U21 AND2X4

Swaps the cell in the PrimeTime session so the change can be written out.

PrimeTime (pt_shell)report_timing -delay_type max

Rechecks setup through the sized cell and its driver.

ICC2 (icc2_shell)size_cell U21 -lib_cell AND2X4

Applies the same size change in the ICC2 layout.

Healthy, Suspicious & Hard-stop Results

Healthy (illustrative): Setup gain of 10 to 30 ps on the path, the driving stage still meeting transition, and no legalization displacement.
Suspicious (illustrative): Gain under 3 ps after upsizing. The cell was not the bottleneck, so revert it and look at the wire or the previous stage.
Hard stop: A new setup or transition violation on the previous stage caused by the larger input pin. Undo the change and fix the driver first.

Common Mistake

The Trap: Upsizing every cell on the worst path to the largest size. The first two cells drive short nets and gain almost nothing, while each larger input pin slows the stage before it. The path improves by 6 ps instead of 30, area grows by 40 um squared and leakage rises on cells that did not need it.

What The Interviewer Is Testing

Understanding the input capacitance cost, not only the drive gain.
Knowing that PrimeTime setup fixing uses sizing alone by default.
Being aware of the difference between size_cell (PT) and size_cell (ICC2).

Follow-up Question & Model Response

"Why can upsizing a cell make the path slower?"

Candidate Model Response: The upsized cell has a larger input capacitance, so the cell driving it sees more load and slows down. If the upsized cell was driving a light load, it only saves a few ps. The extra delay on the previous stage can be larger than that saving. The fix is to size the driver too, or pick a different cell to size.

Practical Example

Tapeout Scenario: On a path failing by -18 ps, U21 is an AND2X1 driving 4 loads over 60 um (illustrative ledger: X1 delay 72 ps, input cap 1.2 fF, leakage 1.0 unit; X4 delay 41 ps, input cap 4.1 fF, leakage 3.6 units). Swapping to AND2X4 saves 31 ps on U21, but its driver, an INVX1, slows by 11 ps from the extra 2.9 fF. The net gain is 20 ps and the path passes at +2 ps. Upsizing the INVX1 to X2 as well recovers 7 ps and ends at +9 ps.

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