What's the real difference between integrated and user-specified clock-gate latency estimation, and which one is the default?

Short Answer

Integrated latency estimation is the default and more accurate method -- the tool estimates and updates clock-gate latency throughout the place_opt flow automatically. User-specified latency uses set_clock_latency directly, where lat_reg is the estimated network latency to ungated registers' clock pins, and lat_cgtoreg is the estimated delay from a CGC's clock pin to the gated register's clock pin -- for CGC clock pins specifically, you use lat_reg minus lat_cgtoreg, not lat_reg alone.

Technical Explanation

• Integrated latency estimation is the default and more accurate method -- the tool estimates and updates clock-gate latency automatically throughout the place_opt flow.
• User-specified latency uses set_clock_latency directly with two distinct values: lat_reg (estimated network latency to ungated registers' clock pins) and lat_cgtoreg (estimated delay from a CGC's clock pin to the gated register's clock pin).
• For ordinary register clock pins, use lat_reg directly. For clock-gating cell clock pins specifically, use lat_reg minus lat_cgtoreg -- not lat_reg alone, which would overstate the CGC's own latency.
• The tool does NOT modify set_clock_latency constraints itself -- tool-estimated values are stored as offsets from user-specified values, visible via write_script -format icc2 but NOT captured in SDC written by write_sdc.

Formula Or Decision Rule

For register clock pins: use lat_reg. For clock-gating cell clock pins: use (lat_reg - lat_cgtoreg), not lat_reg alone.

What To Check

• Warning sign: a CGC clock pin's latency was set using the same lat_reg value as an ordinary register, and downstream timing at that CGC looks systematically off.
• Inspect: confirm whether lat_cgtoreg was actually subtracted for the CGC's clock pin, or whether it was set identically to an ungated register.
• Correct: apply lat_reg minus lat_cgtoreg specifically at CGC clock pins, matching the documented formula, not lat_reg alone.

Healthy, Suspicious & Hard-stop Results

• Expected: CGC clock pins use lat_reg minus lat_cgtoreg, and ordinary register clock pins use lat_reg directly, matching the documented distinction.
• Investigate: every clock pin in the design uses the same latency value regardless of whether it's a CGC or an ordinary register -- that's very likely wrong for the CGC pins specifically.
• Stop: a design's SDC handoff is assumed to carry integrated-estimation latency values -- it does not, since those are offsets not captured by write_sdc.

What The Interviewer Is Testing

Whether you know the precise lat_reg vs lat_cgtoreg distinction, and that write_sdc doesn't capture tool-estimated latency offsets.