For a clock net, when do you choose a wide and spaced NDR over shielding?
From PDVerse PnR Interview Handbook · pdVerse Mentor Guide
Short Answer
For most clock nets, a double-width, double-spacing NDR is the better trade. It lowers resistance, lowers sidewall capacitance and keeps neighbours away, without the capacitance shields add. Shielding is kept for the most sensitive clock nets, where you need the strongest isolation from coupling and can afford the tracks and the extra load.
Technical Explanation
- A default-width clock wire at minimum spacing has high resistance and strong coupling to whatever runs beside it. Its delay changes with neighbour activity, which adds skew and uncertainty.
- A double-width wire halves resistance per micron. Double spacing lowers sidewall capacitance to neighbours sharply, because coupling falls as spacing grows. The router also skips a track next to the wire, so switching signals simply are not there.
- Shielding puts a supply wire on each side of the clock. Coupling to switching signals on that layer drops almost to zero, but the shield wires sit close by, so the clock's own sidewall capacitance goes up.
- That extra capacitance is stable, because shields do not switch, but it is still load. It slows the clock net and costs clock power, which is often a large share of dynamic power.
- Track cost is similar: both take about three tracks. Shielding also needs connections from the shields to the supply, which uses more resources near rails and straps.
- Either way, redundant vias on clock nets help: they lower resistance further and improve reliability. They can be requested in the clock NDR.
- A common split is a wide and spaced NDR on the clock trunk and most branches, and shielding only on specific long, exposed segments near aggressive buses, or on clocks feeding analog-sensitive blocks.
- Whatever is chosen has to be in place before CTS, so the tree is balanced with the real wire resistance and capacitance.
Common Mistake
The Trap: Choosing shielding for every clock net because it gives the lowest crosstalk number. The clock gets slower and burns more power from the added capacitance, and routing tracks disappear across the block. The same crosstalk target could have been met on most nets with a spaced NDR at lower cost.
Follow-up Question & Model Response
"How would you decide which clock segments really need shielding?"
Candidate Model Response: Run signal integrity analysis on the routed clock with a spaced NDR and look for the segments that still show meaningful crosstalk delta delay or noise, usually long parallel runs next to fast, busy nets. Also consider what the clock feeds: clocks into analog, clock domain boundaries or very tight hold paths may deserve more isolation. Shield those segments specifically. Everything else stays on the NDR, which keeps the cost bounded.
Practical Example
Tapeout Scenario: A 1 mm clock trunk is analyzed three ways on the same grid (illustrative). Default wire: 1 track, resistance 1.0x, coupling capacitance 1.0x, crosstalk delta up to 18 ps. Double width, double spacing: 3 tracks, resistance 0.5x, coupling about 0.5x, delta up to 5 ps. Shielded default width: 3 tracks, resistance 1.0x, coupling to switching nets near 0, delta under 1 ps, but total capacitance 1.3x. The team uses the spaced NDR on the trunk and shields one 200 um clock branch, routed as its own net, that runs beside a 64-bit bus, where delta delay was still 4 ps. The shielded branch adds about 2 fF, which CTS absorbs because it is fixed and known. Clock power for the trunk rises by under 1%, far less than shielding the whole trunk would have cost. Both choices live in routing rules set before CTS: the NDR through create_routing_rule with -multiplier_width 2.0 -multiplier_spacing 2.0, the shield through -shield_widths and -shield_spacings, and each assigned to the clock nets that need it with set_clock_routing_rules -nets.
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