What is a non-default routing rule (NDR)?
From PDVerse PnR Interview Handbook · pdVerse Mentor Guide
Short Answer
A non-default routing rule (NDR) is a stricter set of width and spacing rules, and optionally specific vias, that you assign to chosen nets instead of the technology defaults. It is typically used on clocks and other critical nets: a wider wire lowers resistance and extra spacing lowers coupling. Width rules in an NDR are hard constraints and apply to via enclosures too.
Technical Explanation
- The technology file defines default width and spacing for each layer. An NDR overrides them for the nets it is assigned to and is meant to be stricter than the defaults.
- Width can be set as a multiple of the default with
-multiplier_width, or as explicit values per layer with-widths. If you give both,-widthssets the base width and the multiplier is applied to it. - Spacing can be set the same way, with
-multiplier_spacingor-spacings. Extra spacing is what keeps switching neighbours away and reduces crosstalk. - Minimum width rules are hard constraints and apply to all metal of the net, including via enclosures. Make sure the vias used can meet the wider width, or the result is a DRC.
- If the width you ask for is larger than the technology's maximum allowed signal route width, the tool ignores the non-default width, so check the rule took effect.
- NDRs are assigned to clock nets with
set_clock_routing_rulesbefore CTS, and to signal nets withset_routing_rule. - Every NDR costs tracks. A double-width double-spacing wire takes roughly the space of three default tracks, and congestion estimation needs to know about the NDR before routing to plan for it.
What To Check
report_routing_rulesto confirm the rule exists with the widths and spacings you meant.- Which nets carry the rule, especially that clock nets got it before CTS.
- After routing, the actual width of a sample of NDR nets in the layout.
- Congestion in areas with many NDR nets.
Command Checks & Actions
create_routing_rule clk2x -multiplier_width 2.0 -multiplier_spacing 2.0Defines a rule with twice the default width and twice the default spacing.
set_clock_routing_rules -rules clk2xAssigns the rule to clock nets so CTS and clock routing use it.
set_routing_rule -rule clk2x [get_nets fast_bus*]Assigns the rule to selected signal nets.
report_routing_rulesLists the routing rules defined in the block, so you can check what was created.
Healthy, Suspicious & Hard-stop Results
- Healthy (illustrative): The rule reports the intended widths and spacings, clock nets carry it, and routed NDR wires measure at the expected width.
- Suspicious (illustrative): NDR nets showing DRCs at vias, often an enclosure that does not meet the wider width.
- Hard stop: Rule width above the technology maximum, so it was silently ignored, or an NDR spread across so many nets that the block cannot route.
Common Mistake
The Trap: Assigning a clock NDR after CTS instead of before. CTS builds and balances the tree assuming default wires, then routing uses double-width wire with different resistance and capacitance. Skew and latency shift, and CTS has to be rerun. Clock NDRs belong in place before clock_opt.
What The Interviewer Is Testing
- Whether you understand what width and spacing each buy you.
- Do you know NDR width is a hard rule that includes vias?
- A strong answer shows you set the rule at the right point in the flow.
Follow-up Question & Model Response
"Why is double spacing usually more important than double width on a clock?"
Candidate Model Response: Width lowers resistance, which helps long clock wires, but spacing is what controls coupling to neighbours. Coupling capacitance falls quickly as spacing grows, so extra spacing cuts crosstalk delta delay and makes clock timing predictable. It also lowers the sidewall capacitance the net sees. Width without spacing gives a lower-resistance wire that still picks up noise from the next track.
Practical Example
Tapeout Scenario: A block defines clk2x with double width and double spacing and assigns it with set_clock_routing_rules before CTS (illustrative). The default M5 wire is 0.04 um wide at a 0.08 um pitch. The clock wire is now 0.08 um wide with 0.08 um to its neighbours, taking effectively three tracks. On one clock trunk, resistance per micron halves and coupling to neighbours roughly halves. The price is about 4% more M5 usage in the clock spine area, which the congestion map shows as a slightly hotter band that still has no overflow.
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