Why does clock distribution get so much attention in power closure specifically?

Short Answer

The clock distribution network accounts for 30% or more of total dynamic power in modern ASICs -- some sources put it at 30-40% of total chip power -- because clock nets switch at the highest frequency in the design and carry considerable capacitive loading. An optimum clock tree matters for both performance and power, and clock gating substantially reduces this cost.

Technical Explanation

• Clock distribution accounts for 30% or more of total dynamic power in modern ASICs -- some sources put it at 30-40% of total chip power.
• The reason: clock nets switch at the highest frequency in the entire design and carry considerable capacitive loading from every buffer and leaf pin along the way.
• An optimum clock tree therefore matters for both performance (skew/latency) and power at the same time -- they aren't separate concerns with separate trees.
• Clock gating (ICGs) substantially reduces this cost by stopping switching activity on branches that don't need to toggle.
• report_clock_power quantifies the "30% or more of dynamic power" claim with an actual per-clock power breakdown, rather than leaving it as an unverified figure.

Follow-up Question & Model Response

"If clock gating reduces clock power, why doesn't CTS just gate every branch aggressively by default?"

Candidate Model Response: Because gating every branch aggressively risks introducing new functional or timing risk (enable-pin timing, glitch risk, ICG merging correctness) for marginal additional power savings -- CTS balances power reduction against those real risks rather than maximizing gating alone.