What are Decap Cells, and how are they budgeted during placement vs post-route?
From PDVerse PnR Interview Handbook · pdVerse Mentor Guide
Short Answer
Decap (decoupling capacitor) cells act like tiny local batteries sitting right next to your power-hungry logic — when thousands of cells switch at once and draw a sudden current surge, the decap discharges its stored charge locally instead of making that current travel all the way back through the power grid, which is what causes dynamic IR drop. Physically, a decap cell is usually just an empty inverter shell wired backwards as a capacitor — PMOS gate tied to VSS, NMOS gate tied to VDD — so it behaves as a parallel-plate capacitor rather than an active logic gate.
Technical Explanation
- Decap (decoupling capacitor) cells act like tiny local batteries sitting right next to your power-hungry logic — when thousands of cells switch at once and draw a sudden current surge, the decap discharges its stored charge locally instead of making that current travel all the way back through the power grid, which is what causes dynamic IR drop.
- Physically, a decap cell is usually just an empty inverter shell wired backwards as a capacitor — PMOS gate tied to VSS, NMOS gate tied to VDD — so it behaves as a parallel-plate capacitor rather than an active logic gate.
- There are two very different insertion strategies, and mixing them up is a common mistake: pre-placement decaps are deliberately placed early, close to high-switching blocks like CPU cores, DSP ALUs, or big clock buffer trees, because that's exactly where the current surges will happen.
- Post-route filler decaps are the opposite — they're stuffed into whatever standard-cell row space is left empty after detail routing is clean, essentially "free" capacitance from unused area rather than a targeted placement decision.
- Don't over-insert them, though — decap cells have thin gate oxides, which means real gate-tunneling leakage. Pushing decap density too high can add 15–30% to total standby leakage power, so it's a genuine power trade-off, not a free lunch.
- The practical takeaway: budget decaps deliberately near known high-di/dt logic during floorplanning/placement, then let the remaining rows fill naturally post-route — don't treat "more decaps everywhere" as automatically better.
Common Mistake
The Trap: Filling 100% of empty row space with decaps on a low-power mobile chip. The gate oxide tunneling leakage from excess decaps will blow past standby battery power limits.
Follow-up Question & Model Response
"What is the difference between standard filler cells and decap filler cells?"
Candidate Model Response: Standard fillers only contain N-well and poly layers to maintain DRC continuity. Decap fillers include active MOS gate structures to add decoupling capacitance.
Practical Example
Inserting Decap Cells Pre-Placement:
# Synopsys ICC2: Add pre-placement decap cells near clock buffers
add_decap_cells -lib_cells [get_lib_cells */DECAP*] -target_capacitance 500pF
# Post-route filler insertion with mixed decaps and standard fillers
create_stdcell_fillers -lib_cells [get_lib_cells */DECAP* */FILL*]Physical Design & Planning Handbook
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