BeginnerQuestion 160 of 187Source: Synopsys IC Validator User Guide: IC Validator Basics (Using PXL Runset Encryption)

What is a DRC runset (deck), and who owns it?

From PDVerse PnR Interview Handbook · pdVerse Mentor Guide

Short Answer

A runset, often called a deck, is the program IC Validator executes: layer assignments, database checks and every design rule coded as PXL functions. The foundry writes and qualifies it for a specific process node and version, and the design team runs it without editing the rules. Checking against the wrong node, the wrong version or a locally modified copy is a real way to tape out a violating layout.

Technical Reference DiagramWhat is a DRC runset (deck), and who owns it?
Flow from the foundry design rule manual to a foundry-qualified IC Validator runset, then to a designer-side icv run on the GDS and finally to the RESULTS and LAYOUT_ERRORS files, with a version tag on the runset box.

Technical Explanation

  • The IC Validator guide describes a runset as holding layout database specifics, general options, layer assignments, database checks such as snap and grid checks, and the DRC, ERC, fill or LVS checks themselves. Every IC Validator run executes from a runset.
  • The foundry owns the rule content. It translates its design rule manual into runset code and qualifies that runset against test structures. The values in it are confidential and node-specific, which is why interview answers should never quote a real rule number.
  • Foundries can encrypt parts of a runset with pxlcrypt (ICV). Encrypted functions are reported as "encrypted function" in the summary file, so you can see that a check ran and how much memory it used, but not how it is coded.
  • The designer owns the run setup: which GDS or OASIS to read, the top cell, the layer map, and the switches the foundry exposes, such as optional rule groups. Those switches are documented by the foundry for each runset release.
  • There are usually several decks for one node: DRC, LVS, antenna, metal fill and sometimes DFM recommended rules. Each has its own version. The metal-fill runset used by signoff_create_metal_fill (ICC2) is a different file from the DRC runset set in signoff.check_drc.runset (ICC2).
  • Runsets change during a node's life. A new release can tighten a spacing rule or add a check. Tapeout signoff must use the version the foundry lists for that tapeout, and the version should be recorded next to the clean result.
  • The runset also defines layer assignments, which map stream layer and datatype numbers to the layers the rules act on. When a layer mapping file substitutes those numbers, cell.sum (ICV) reports the substitution under each assign statement, which is the place to confirm a layer was read at all.
  • Rule names in results files come from the runset comments. cell.RESULTS (ICV) lists per-rule counts only when the runset asks for verbose results, so what you see is partly decided by the deck.

Common Mistake

The Trap: Copying the DRC runset into the project directory months earlier and pointing every run at that copy. The foundry releases a new version with an updated via enclosure rule, the team never switches, and the block is "clean" against a deck the foundry no longer accepts. The foundry's own check at tapeout intake flags hundreds of violations, and the block goes back for a routing fix.

Follow-up Question & Model Response

"Can a designer waive or change a DRC rule in the runset?"

Candidate Model Response: The designer should not edit rule code. If a violation is believed to be safe, the process is a waiver: the specific violation, location and reason are documented and approved by the foundry or the internal signoff owner. IC Validator supports error classification so that approved waivers are tracked instead of silently removed. Editing the deck to make an error disappear removes the evidence and usually gets caught at foundry intake.

Practical Example

Tapeout Scenario: A team has three runsets for one node: DRC v1.3, LVS v1.2 and fill v1.1 (illustrative version numbers). Mid-project the foundry issues DRC v1.4 with one tightened enclosure rule. Rerunning the block with v1.4 turns a clean RESULTS: CLEAN (ICV) into RESULTS: NOT CLEAN (ICV) with 212 enclosure violations on one via layer, all on a single via type the router preferred. Swapping that via definition and rerouting the affected nets clears them in one day. Finding them at foundry intake would have cost a week. The team then adds the runset version to the header of every signoff report so a stale deck is visible at a glance.

PnR Flow Mentor Guide

Read the complete 8-chapter PnR Flow Mentor Guide free on the web — library setup through placement, clock tree synthesis, routing, chip finishing, hierarchical implementation, and ECO, all the way to stream-out.

PnR Flow Physical Design Mentor Guide — eight chaptersPnR Flow Mentor GuideEight chapters, library setup through to stream-out. →