What's the difference between DRC, LVS and ERC?
From PDVerse PnR Interview Handbook · pdVerse Mentor Guide
Short Answer
DRC checks the layout geometry against the foundry manufacturing rules. LVS checks that the devices and connections extracted from the layout match the reference netlist. ERC checks for electrically unsafe connections, such as floating gates or untied wells, that can exist even when layout and netlist agree.
Technical Explanation
- DRC compares shapes with rules. There is no netlist involved. The runset measures width, spacing, enclosure, area, density and via rules layer by layer, and each violation is a location and a rule name. Results land in
cell.LAYOUT_ERRORS(ICV) with the summary incell.RESULTS(ICV), whose header readsRESULTS: CLEAN(ICV) orRESULTS: NOT CLEAN(ICV). - LVS compares two netlists. IC Validator extracts transistors and nets from the layout, then matches them against the schematic or Verilog-derived reference. The header line is
LVS Compare Results: PASS | FAIL(ICV), and the detail for debugging is incell.LVS_ERRORS(ICV). Typical failures are shorts, opens, missing devices and port mismatches. - ERC checks electrical properties of the connectivity itself. The runset looks for gates with no driver, wells or substrate regions without a tie, and similar hazards. It needs the extracted connectivity, so it usually runs inside the same deck flow as LVS extraction, but it does not compare against a reference.
- Each check answers a different question. DRC asks "can the fab build this?" LVS asks "is this the circuit we designed?" ERC asks "is this circuit safe to power up?" None of them covers the others.
- A layout can pass DRC and fail LVS: two nets touch through a legal-width strap, so every shape is rule-clean, yet two signals are shorted. A layout can pass LVS and fail DRC: connectivity matches but two wires are 10 nm too close.
- A layout can pass LVS and fail ERC. If an unused input is left unconnected in both the reference netlist and the layout, the comparison matches, but the gate floats. The next page, on how LVS can pass while ERC fails, walks through that case.
- All three are foundry-owned rules. The designer runs the foundry runset in IC Validator; the rule values themselves are confidential and change from node to node.
- ICC2 has earlier, lighter versions of two of them.
signoff_check_drc(ICC2) runs IC Validator DRC on the design library, andcheck_lvs(ICC2) looks for routing-level shorts, opens and floating shapes. Neither extracts transistors, so neither replaces the IC Validator LVS run on the final stream, and ERC still comes from the foundry runset.
Common Mistake
The Trap: Reading "LVS PASS" as proof the layout is clean. The cell.RESULTS (ICV) file for an LVS run also carries a second header line, DRC and Extraction Results: CLEAN | NOT CLEAN (ICV). A junior sees PASS on the first line, misses NOT CLEAN on the second, and ships a layout with extraction errors from a bad text label that later hides a real port short.
Follow-up Question & Model Response
"Which of the three would catch a VDD-to-VSS short inside the power grid?"
Candidate Model Response: LVS catches it, because the extracted layout shows one merged net where the reference netlist has two supply nets. DRC usually does not, since the overlapping shapes can each be rule-legal. ERC may flag related issues but is not the primary check. In practice I also run the ICC2 check_lvs (ICC2) pre-check with the short check enabled before stream-out, because a PG short is much cheaper to find in the routing database than after a full IC Validator run.
Practical Example
Tapeout Scenario: One block, three results (illustrative). DRC: RESULTS: NOT CLEAN (ICV) with 12 violations, 9 of them minimum spacing on M2 near a macro pin. LVS: LVS Compare Results: FAIL (ICV), one short between net n_418 and scan_en caused by a misplaced via. ERC: two floating-gate flags on unused inputs of a spare cell. Fixing the via clears LVS and 1 of the DRC errors; the spacing errors need a route change; the ERC flags need tie-off cells. Three reports, three different fixes. The order matters too: the LVS short goes first because it can hide other connectivity errors, then ERC, and DRC last because every route change can create new spacing errors.
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