Why check driving cell, input transition, and output load?
From PDVerse PnR Interview Handbook · pdVerse Mentor Guide
Short Answer
These constraints model the electrical environment needed for meaningful cell delay and slew calculation at ports.
Technical Explanation
The input driver controls incoming slew, and the output load controls how hard an output must work. Both affect calculated cell delay even before physical implementation begins.
What To Check
• Warning sign: Ports have timing delays but no credible slew or load assumptions. • Inspect: Start with one named object in the report and trace it to the netlist, library, or SDC statement that created it. • Correct: Apply the project-approved driving or transition and load model, then inspect port design-rule information.
Command Checks & Actions
• report_ports -drive [get_ports *]: shows boundary constraints and electrical assumptions
• report_ports -design_rule [get_ports *]: shows boundary constraints and electrical assumptions
Run the commands in order. Each line answers a separate part of the check.Healthy, Suspicious & Hard-stop Results
• Expected: These constraints model the electrical environment needed for meaningful cell delay and slew calculation at ports. • Investigate: Ports have timing delays but no credible slew or load assumptions. • Stop before floorplanning when required logic or timing coverage is missing or unexplained. Apply the project-approved driving or transition and load model, then inspect port design-rule information.
Common Mistake
Do not assume the check passed just because ICC2 continued: Ports have timing delays but no credible slew or load assumptions. Fix or narrowly justify the named objects, then rerun the same command.
What The Interviewer Is Testing
Be ready to explain why this matters before floorplanning: Ports have timing delays but no credible slew or load assumptions.
Practical Example
Symptom: Ports have timing delays but no credible slew or load assumptions. Corrective path: Apply the project-approved driving or transition and load model, then inspect port design-rule information.
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