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What do input and output delays describe?

From PDVerse PnR Interview Handbook · pdVerse Mentor Guide

Short Answer

They describe external timing relative to a clock; they are not delays of the block's input or output buffers.

Technical Explanation

Input and output delays describe time spent outside the block. They connect the block-level timing model to the device that launches data into it or captures data from it.

What To Check

• Warning sign: Only maximum values are supplied or ports reference the wrong clock edge. • Inspect: Start with one named object in the report and trace it to the netlist, library, or SDC statement that created it. • Correct: Return to the interface budget, apply required min/max and rise/fall intent, and review boundary timing paths.

Command Checks & Actions

• report_ports -input_delay [get_ports *]: shows boundary constraints and electrical assumptions • report_ports -output_delay [get_ports *]: shows boundary constraints and electrical assumptions Run the commands in order. Each line answers a separate part of the check.

Healthy, Suspicious & Hard-stop Results

• Expected: They describe external timing relative to a clock; they are not delays of the block's input or output buffers. • Investigate: Only maximum values are supplied or ports reference the wrong clock edge. • Stop before floorplanning when required logic or timing coverage is missing or unexplained. Return to the interface budget, apply required min/max and rise/fall intent, and review boundary timing paths.

Common Mistake

Do not assume the check passed just because ICC2 continued: Only maximum values are supplied or ports reference the wrong clock edge. Fix or narrowly justify the named objects, then rerun the same command.

What The Interviewer Is Testing

Be ready to explain why this matters before floorplanning: Only maximum values are supplied or ports reference the wrong clock edge.

Practical Example

Symptom: Only maximum values are supplied or ports reference the wrong clock edge. Corrective path: Return to the interface budget, apply required min/max and rise/fall intent, and review boundary timing paths.

Original guide diagramWhat do input and output delays describe?
What do input and output delays describe?, illustrating the physical design concept.