What makes a generated clock different from a primary clock?
From PDVerse PnR Interview Handbook · pdVerse Mentor Guide
Short Answer
A generated clock derives its frequency, phase, or edges from a master/source relationship in the implemented logic.
Technical Explanation
A primary clock begins at a design source such as an input port. Its period and waveform define the time reference used by downstream paths.
What To Check
• Warning sign: The generated clock exists by name but has the wrong source pin or divide relationship. • Inspect: Start with one named object in the report and trace it to the netlist, library, or SDC statement that created it. • Correct: Correct the source/master and transformation in the SDC, then prove a valid path to representative sinks.
Command Checks & Actions
• report_clocks: shows clock definitions and relationships
• check_timing -include {generated_clock no_clock}: finds missing or inconsistent timing setup
Run the commands in order. Each line answers a separate part of the check.Healthy, Suspicious & Hard-stop Results
• Expected: A generated clock derives its frequency, phase, or edges from a master/source relationship in the implemented logic. • Investigate: The generated clock exists by name but has the wrong source pin or divide relationship. • Stop before floorplanning when required logic or timing coverage is missing or unexplained. Correct the source/master and transformation in the SDC, then prove a valid path to representative sinks.
Common Mistake
Do not assume the check passed just because ICC2 continued: The generated clock exists by name but has the wrong source pin or divide relationship. Fix or narrowly justify the named objects, then rerun the same command.
What The Interviewer Is Testing
Be ready to explain why this matters before floorplanning: The generated clock exists by name but has the wrong source pin or divide relationship.
Practical Example
Symptom: The generated clock exists by name but has the wrong source pin or divide relationship. Corrective path: Correct the source/master and transformation in the SDC, then prove a valid path to representative sinks.
Continue practising