What must be checked for a primary clock?
From PDVerse PnR Interview Handbook · pdVerse Mentor Guide
Short Answer
Verify its source object, name, period, waveform, mode visibility, and reach to intended sequential clock pins.
Technical Explanation
A primary clock begins at a design source such as an input port. Its period and waveform define the time reference used by downstream paths.
What To Check
• Warning sign: A port named clk exists but no clock object is created, or the waveform is wrong. • Inspect: Start with one named object in the report and trace it to the netlist, library, or SDC statement that created it. • Correct: Correct create_clock in the owning SDC and confirm the reported clock and representative clock-pin timing.
Command Checks & Actions
• report_clocks: shows clock definitions and relationships
• check_timing -include {no_clock}: finds missing or inconsistent timing setup
Run the commands in order. Each line answers a separate part of the check.Healthy, Suspicious & Hard-stop Results
• Expected: Verify its source object, name, period, waveform, mode visibility, and reach to intended sequential clock pins. • Investigate: A port named clk exists but no clock object is created, or the waveform is wrong. • Stop before floorplanning when required logic or timing coverage is missing or unexplained. Correct create_clock in the owning SDC and confirm the reported clock and representative clock-pin timing.
Common Mistake
Do not assume the check passed just because ICC2 continued: A port named clk exists but no clock object is created, or the waveform is wrong. Fix or narrowly justify the named objects, then rerun the same command.
What The Interviewer Is Testing
Be ready to explain why this matters before floorplanning: A port named clk exists but no clock object is created, or the waveform is wrong.
Practical Example
Symptom: A port named clk exists but no clock object is created, or the waveform is wrong. Corrective path: Correct create_clock in the owning SDC and confirm the reported clock and representative clock-pin timing.
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