What is the difference between importing and linking a netlist?
From PDVerse PnR Interview Handbook · pdVerse Mentor Guide
Short Answer
Import creates design objects from the Verilog; linking resolves every instantiated reference against the available design and library context.
Technical Explanation
Reading Verilog creates names and connections. Linking is the next step: ICC2 finds the real definition for every cell or lower-level module that was instantiated.
What To Check
• Warning sign: The Verilog reads successfully while instances remain unresolved or black-boxed unintentionally. • Inspect: Start with one named object in the report and trace it to the netlist, library, or SDC statement that created it. • Correct: Correct the reference setup or source netlist and link again; do not create dummy cells to silence the problem.
Command Checks & Actions
• read_verilog <netlist.v>: imports the gate-level connectivity
• link_block: resolves instantiated references
• report_unbound: lists objects that did not resolve
Run the commands in order. Each line answers a separate part of the check.Healthy, Suspicious & Hard-stop Results
• Expected: Import creates design objects from the Verilog; linking resolves every instantiated reference against the available design and library context. • Investigate: The Verilog reads successfully while instances remain unresolved or black-boxed unintentionally. • Stop before floorplanning when required logic or timing coverage is missing or unexplained. Correct the reference setup or source netlist and link again; do not create dummy cells to silence the problem.
Common Mistake
Do not assume the check passed just because ICC2 continued: The Verilog reads successfully while instances remain unresolved or black-boxed unintentionally. Fix or narrowly justify the named objects, then rerun the same command.
What The Interviewer Is Testing
Be ready to explain why this matters before floorplanning: The Verilog reads successfully while instances remain unresolved or black-boxed unintentionally.
Practical Example
Symptom: The Verilog reads successfully while instances remain unresolved or black-boxed unintentionally. Corrective path: Correct the reference setup or source netlist and link again; do not create dummy cells to silence the problem.
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