ExpertQuestion 107 of 50Source PDF page undefined

A bulk input-delay command constrained the clock port. What is the impact?

From PDVerse PnR Interview Handbook · pdVerse Mentor Guide

Short Answer

It models the clock port as ordinary data and can create misleading boundary paths or constraints; selector scope is defective.

Technical Explanation

For an input port, min and max describe the earliest and latest external arrival. Both must point to the correct reference clock and edge.

What To Check

• Warning sign: report_ports shows input delay on clocks, resets, or non-data controls. • Inspect: Keep at least two possible causes open, then use one named object and the active mode or scenario to separate them. • Correct: Replace the wildcard with explicit data-port collections, reload the SDC cleanly, and verify membership.

Command Checks & Actions

• report_ports -input_delay [get_ports *]: shows boundary constraints and electrical assumptions • report_clocks: shows clock definitions and relationships Run the commands in order. Each line answers a separate part of the check.

Healthy, Suspicious & Hard-stop Results

• Expected: It models the clock port as ordinary data and can create misleading boundary paths or constraints; selector scope is defective. • Investigate: report_ports shows input delay on clocks, resets, or non-data controls. • Stop before floorplanning when required logic or timing coverage is missing or unexplained. Replace the wildcard with explicit data-port collections, reload the SDC cleanly, and verify membership.

Common Mistake

Do not assume the check passed just because ICC2 continued: report_ports shows input delay on clocks, resets, or non-data controls. Fix or narrowly justify the named objects, then rerun the same command.

What The Interviewer Is Testing

Be ready to explain why this matters before floorplanning: report_ports shows input delay on clocks, resets, or non-data controls.

Follow-up Question & Model Response

Model response: “I would save the report, inspect one affected object in the correct block and scenario, and make or request this correction: Replace the wildcard with explicit data-port collections, reload the SDC cleanly, and verify membership. Then I would reopen the clean checkpoint and rerun the same evidence.”

Practical Example

Symptom: report_ports shows input delay on clocks, resets, or non-data controls. Corrective path: Replace the wildcard with explicit data-port collections, reload the SDC cleanly, and verify membership.

Original guide diagramA bulk input-delay command constrained the clock port. What is the impact?
A bulk input-delay command constrained the clock port. What is the impact?, illustrating the physical design concept.