Why are input and output delays needed, and what do min and max mean?
From PDVerse PnR Interview Handbook · pdVerse Mentor Guide
Short Answer
Input and output delays describe timing outside the block boundary relative to a reference clock. Maximum and minimum values expose the late and early interface behavior needed for setup and hold analysis.
Technical Explanation
An input delay represents when externally launched data can reach an input port. The remaining timing budget must accommodate the internal data path and capture requirements. An output delay represents the external timing requirement beyond the output port, including the appropriate receiver and connection budget. It is not the delay of the internal output buffer. For a simplified same-edge interface with a 10 ns period and a maximum input delay of 3 ns, approximately 7 ns remains before subtracting internal capture setup, uncertainty, and relevant clock effects. With a maximum output delay of 2 ns, the simplified internal output budget is approximately 8 ns. These are teaching budgets, not complete signoff equations; clock latency relationships and interface conventions must be modeled consistently. Minimum values matter because data that arrives too early can violate hold requirements. Output minimum delay can be negative under common receiver-hold conventions; the correct sign follows the interface timing equation, not a rule that every delay must be positive. Use the interface specification and explicit min/max values where required. Verify the reference clock, reference edge, and whether latency has already been included.
Common Mistake
Using the clock period itself as both input and output delay, or inventing min values by copying max values.
Follow-up Question & Model Response
Why use a virtual clock? It can represent the external timing reference without requiring that clock to propagate through a physical port in the block.
Practical Example
If upstream data arrives between 0.5 ns and 3 ns after launch, model that range with the appropriate minimum and maximum input constraints. Modeling only the late arrival leaves the early-arrival assumption inadequately specified.
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