How do you judge whether IR drop is acceptable?
From PDVerse PnR Interview Handbook · pdVerse Mentor Guide
Short Answer
IR drop is acceptable when every loss the cell can see fits inside the voltage margin the library was characterised for. The rule is: grid drop (Vmax - Vmin on the supply net), plus ground rise, plus external supply variation, must be less than the gap between nominal VDD and the worst-case voltage used in the standard-cell library. If the slow corner is characterised at 0.72 V for a 0.80 V supply, everything together must fit in 80 mV.
Technical Explanation
- The budget comes from the library, not the IR tool. Timing signoff assumes cells run at the corner voltage, so any loss below it is outside what timing checked.
- Vmax is the highest node voltage on the net, at the supply points; Vmin is the lowest, at the worst cell. Their difference is the on-die drop. Ground rise on VSS adds to it, because the cell sees VDD minus VSS.
- External supply variation is regulator tolerance and board or package loss. It is spent before the current even reaches the die, so it comes off the top of the budget.
- Teams split the margin up front: a share for the supply, a share for static on-die drop and a share for dynamic dips. The numbers are project decisions and vary by product; the ones on this page are illustrative.
- Static analysis is optimistic by construction. It assumes decap smooths the peaks and leaves out local dynamic effects, so a static result that uses the whole budget leaves nothing for the real dips. Keep enough decap and check dynamic against its own share.
- Judge per instance, not per map colour.
report_rail_result -type effective_voltage_drop(ICC2) lists the effective drop at each cell PG pin. Both references describevoltage_drop_or_riseas dynamic violations, so use it with-thresholdon a dynamic result.
Formula Or Decision Rule
(Vmax - Vmin) + dV_ground_rise + dV_supply_variation < VDD_nom - V_lib_worst- Example split (illustrative):
80 mV total = 30 mV supply + 30 mV static on-die + 20 mV extra for dynamic - Pass per instance when
dV_VDD + dV_VSSat its pins stays inside the on-die share.
What To Check
- The library worst-case voltage for the corner you sign off, and the supply tolerance given by the system team.
- Worst VDD drop and worst VSS rise, and whether they occur at the same cells.
- The count of instances over the on-die share, not only the single worst value.
- Whether the offenders sit on timing-critical paths or clock buffers.
- Dynamic dips checked against their own share, not against the static number.
Command Checks & Actions
analyze_rail -voltage_drop static -nets {VDD VSS}Runs static voltage drop on both supply nets through RedHawk Fusion.
report_rail_result -type effective_voltage_drop -supply_nets {VDD VSS} -limit 100 inst_effvd.rptWrites the 100 worst effective drops per cell PG pin, sorted descending.
report_rail_result -type voltage_drop_or_rise -supply_nets {VDD VSS} -threshold 0.05 dvd.rptOn a dynamic result, keeps only values above 50 mV, the full on-die share here.
perform analysis -staticStandalone static run; the log lists the five worst drops per power and ground net.
Healthy, Suspicious & Hard-stop Results
- Healthy (illustrative): Supply 30 mV, worst VDD drop 18 mV, worst VSS rise 9 mV: total 57 mV against 80 mV.
- Suspicious (illustrative): Total inside budget but on-die drop using 29 of its 30 mV, leaving nothing for dynamic effects, or a few hundred instances within 2 mV of the limit.
- Hard stop: Any instance whose VDD drop plus VSS rise exceeds the on-die share, or a static result that already consumes the dynamic share.
Common Mistake
The Trap: Comparing the worst VDD drop alone against 5% of VDD and forgetting that the supply tolerance was already spent. A 38 mV drop looks fine against 40 mV, but with 30 mV of supply variation and 12 mV of ground rise the cells see 80 mV of loss, right at the edge of the 0.72 V corner with no room for dynamic dips, and the margin shows up as failures at the slow tester corner.
What The Interviewer Is Testing
- Whether the candidate ties the IR budget to the library corner voltage instead of a floating percentage.
- Knowing that ground rise and supply variation count against the same margin.
- Awareness that static results are optimistic.
Follow-up Question & Model Response
"What do you do if the budget is exceeded in one small region only?"
Candidate Model Response: First confirm it is real: check the map for a missing via or a floating tap that would explain a sharp local step. If the grid is intact, add straps or vias locally, or spread the high-current cells that cause it. If the region holds only non-critical logic, some teams run timing with the reduced voltage on those cells to show the paths still pass, but that is a documented exception, not the default.
Practical Example
Tapeout Scenario: (illustrative) 0.80 V nominal, library slow corner at 0.72 V, so 80 mV of margin. The system team takes 30 mV for regulator and package. Static analysis shows 18 mV worst VDD drop and 9 mV worst VSS rise at one cluster: 27 mV on-die, inside its 30 mV share, and 30 + 18 + 9 = 57 mV in total. Dynamic analysis adds a 29 mV dip there, over its 20 mV share, so the total is 86 mV and fails by 6 mV. Adding decap brings the dip to 19 mV and the total to 76 mV, with every share met.
PnR Flow Mentor Guide
Master the Physical Design Implementation Flow
Read the complete 8-chapter PnR Flow Mentor Guide free on the web — library setup through placement, clock tree synthesis, routing, chip finishing, hierarchical implementation, and ECO, all the way to stream-out.
Continue practising