What is IR drop, and why does it hurt timing?

Short Answer

IR drop is the voltage lost across the resistance of the power grid when current flows through it, V = I x R added up along the path from the pad or bump to each cell's power pin. The ground side does the same in reverse, so VSS at the cell sits slightly above zero. The cell therefore runs on less than the nominal supply, its drive current falls, and paths that were timed at the library voltage come out slower than signoff assumed.

Technical Explanation

• Think of the grid as a resistor ladder: pad, top straps, via stacks, lower straps, rails, cell pin. Every segment has resistance from its sheet resistance, length and width. The current of every cell downstream flows through the upstream segments, so the drop builds up toward the far, busy cells.
• The VSS network has the same resistance, and the same current returns through it, so the local ground rises. The cell sees the difference between its VDD pin and its VSS pin, which RedHawk calls effective voltage (Vdd - Vss). Checking only the VDD side misses part of the loss.
• Cell delay tables are characterised at a fixed supply per corner. When the real supply at the pin is lower, the transistors switch with less overdrive and the stage is slower, so setup margin shrinks. At low-voltage nodes the headroom above threshold is small, which makes the delay more sensitive to each millivolt.
• Clock buffers suffer too. If the launch branch sits in a low-drop area and the capture branch in a hotspot, the capture clock arrives late and the skew changes. That can hurt hold as well as setup, which is why IR drop is not only a setup problem.
• The usual causes are too few or too narrow straps, missing vias between layers, clusters of high-activity cells, and long distance from the nearest supply point. A missing via adds resistance in exactly one spot and shows up as a sudden step on the IR map.
• Temperature matters as well. RedHawk scales metal resistance with temperature through the tech-file coefficients, so a hot region has higher R and a larger drop for the same current.
• In ICC2 the drop is computed through RedHawk Fusion with analyze_rail -voltage_drop static -nets {VDD VSS} (ICC2). Static analysis uses average currents; dynamic analysis follows the instantaneous current and usually shows deeper, local dips.

Formula Or Decision Rule

• Drop at a cell: V_drop = sum(I_k x R_k) over the segments k from the supply point to the pin, where I_k is all current flowing through segment k.
• Segment resistance: R = R_sheet x L / W.
• Voltage the cell sees: V_eff = VDD_nom - dV_VDD - dV_VSS.
• Decision rule: dV_VDD + dV_VSS must fit inside the share of the voltage budget given to on-die drop (budget values are project decisions; for example 5% of VDD, illustrative).

Follow-up Question & Model Response

"If IR drop is just resistance, why not make every strap wider?"

Candidate Model Response: Wider straps lower R, but they take routing tracks on the layers you need for signals, which raises congestion and coupling. Wide PG on lower layers also blocks pin access to cells. Width does not help when the real cause is a missing via, a badly placed supply point or a local current cluster. The better approach is to read the map, add straps or vias where the drop is, spread high-current cells and add decap where the problem is dynamic.