What are MiM capacitors, and how are they inserted?

Short Answer

A MiM capacitor is two special conducting plates with an insulator between them, built between two regular metal layers such as M8 and M9, and usually connected between power and ground to steady the supply. Because it sits in the upper stack, it adds decoupling without using standard-cell row area. In ICC2, create_mim_capacitor_array (ICC2) places an array of a MiM library cell at a fixed x and y pitch, and by default it ignores standard cells, macros, placement blockages and voltage areas.

Technical Explanation

• The guide's example stack puts MBOT and MTOP layers between M8 and M9, with mask names mimbottom and mimtop for the plates and viaMimbottom and viaMimtop for the vias. The technology file and signoff runsets must define them.
• MiM capacitance adds to decap cells and to the grid's own capacitance. It helps dynamic voltage drop and supply noise, and does nothing for static IR drop, which depends on grid resistance and average current.
• The cell's size is usually customised to fit the power strap geometry of a specific power plan, so the array pitch follows the strap pitch. That is why -lib_cell (ICC2), -x_increment (ICC2) and -y_increment (ICC2), the distances between cell centres, are all required.
• By default the array covers the whole block in R0 orientation, with instances named mimcap!library_cell_name!number. -boundary (ICC2) limits it to a single rectangular or rectilinear region, -orientation (ICC2) changes every cell in the array, and -prefix (ICC2) tags a run.
• The command does not consider standard cells, macros, placement blockages or voltage areas, and the command reference adds PG network routes to that list. Keeping the array away from macros and other-supply voltage areas is your job.
• The command reference also lists create_mim_layer_capacitors (ICC2), which builds 2-plate or 3-plate MiM shapes. create_mim_layer_capacitors -mim_layer_net plates -rv_layer rv_layer -exclude_overlap_net_type {clock signal} (ICC2) skips areas over clock or signal nets; the first two options are required.

What To Check

• MiM plate and via layers exist in the technology file and in the layer maps used by signoff tools.
• Array pitch matches the strap pitch so every cell lands on its straps.
• No cells over macros, keepout areas or voltage areas with a different supply.
• check_pg_connectivity (ICC2), DRC and LVS clean after insertion.
• Dynamic IR before and after, inside the regions the array covers.

Healthy, Suspicious & Hard-stop Results

• Healthy (illustrative): Every array cell lands on its straps, DRC and LVS are clean on the MiM layers, and the worst dynamic drop in the covered region falls, for example from 82 mV to 67 mV.
• Suspicious (illustrative): Cells over a macro or across a voltage-area edge, or almost no change in dynamic drop, which means the noise is local and needs decap next to the cells.
• Hard stop: LVS shows a VDD-VSS short through a MiM via, or the MiM layers are missing from a layer map so signoff never checked them.

What The Interviewer Is Testing

• Knowing MiM is a process feature in the upper metal stack, not a standard cell in the rows.
• Knowing what the command ignores and why the pitch must follow the strap pattern.
• Placing MiM correctly in the IR story: dynamic noise, not static drop.

Follow-up Question & Model Response

"MiM or more decap fillers: how do you choose?"

Candidate Model Response: Decap fillers sit right beside switching cells, so they answer very local current demand, but they cost row area and add leakage. MiM capacitors cost no row area and can add a lot of capacitance, but they sit further away, reached through the grid and vias, and they need the process option. I use decap fillers for local hotspots and MiM for broad supply noise when the process offers it.