Why can't you just close timing mode by mode independently and call the design done?
From PDVerse PnR Interview Handbook · pdVerse Mentor Guide
Short Answer
SoCs operate in multiple modes (active, sleep, test) sharing the same logic, each needing its own constraints -- sleep mode may use a different supply voltage or clock frequency, for instance. Fixing timing in one mode can genuinely reopen violations in another, because the same physical cells and paths are shared across modes -- a fix that helps mode A's timing can change delay in a way that hurts mode B's, since they're not independent designs, they're the same design analyzed under different constraint sets.
Technical Explanation
- SoCs operate in multiple modes (active, sleep, test) sharing the same underlying logic -- each mode needs its own constraints, since e.g. sleep mode may use a different supply voltage or clock frequency than active mode.
- Fixing timing in one mode can genuinely reopen violations in another mode, because the same physical cells and paths are shared -- they aren't independent designs, they're one design analyzed under different constraint sets.
- A fix (cell resize, buffer insertion) that helps mode A's timing changes real physical delay, and that changed delay is what mode B's analysis sees too -- there's no way to change delay for "just one mode."
- This is exactly why modern STA tools support multimode analysis (create_mode, read_sdc -mode) rather than closing each mode as a fully separate, sequential exercise.
Common Mistake
The Trap: Closing timing mode by mode sequentially and declaring the design done after the last mode passes, without re-checking earlier modes that fixes made in later modes might have silently reopened.
Follow-up Question & Model Response
"What would a genuinely mode-safe fix look like, given that any physical change affects every mode simultaneously?"
Candidate Model Response: A fix that's verified across ALL active modes/scenarios after being applied, not just the mode it was intended for -- since the same physical change is seen by every mode's analysis, the only way to know it's safe is to check it against all of them, not assume success in one mode implies safety in the others.
Practical Example
Debug Scenario: A cell upsized to fix an active-mode setup violation is later found to have introduced a new sleep-mode hold violation -- the same physical resize, analyzed under sleep mode's different voltage/frequency constraints, produced a different (and this time negative) timing outcome.
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