IntermediateQuestion 24 of 84Source PDF page undefined

The design loads and timing looks clean. Why can the inputs still be wrong?

From PDVerse PnR Interview Handbook ยท pdVerse Mentor Guide

Short Answer

Successful import proves that the tool accepted data; clean timing proves only that the analyzed constraints passed. Neither proves that the files represent the intended chip or that all required cases were analyzed.

Technical Explanation

Consider a missing generated clock: downstream paths may never receive the intended clock-based checks. Consider an inactive slow scenario: reports can omit the operating condition that would fail. An overly broad false path can remove a difficult interface. A nominal library accidentally substituted for a slow model can make results look plausible and optimistic at the same time. Physical and power errors can also survive a timing summary. An old macro abstract can give the wrong pin geometry. A mismatched DEF can leave important objects unannotated. A power-domain strategy applied at the wrong hierarchy scope can fail to protect a shutdown boundary. These are different failure classes and need targeted evidence rather than one pass/fail badge. Debug by comparing expectations with reports: design counts, required clocks, constrained interfaces, active analysis types, library/model selection, RC assignments, macro geometry, and power-intent checks. Inspect a few representative critical paths to see the actual scenario, cells, edges, and parasitics. Reconcile unexplained changes against the last validated handoff before starting optimization.

Common Mistake

Treating 'zero violations' as a universal proof of correctness, or adjusting optimization effort before checking the problem definition.

Follow-up Question & Model Response

What is the strongest readiness evidence? A consistent package plus reproducible reports showing that the intended objects, conditions, and checks are present.

Practical Example

Yesterday the design had eight clocks; today's report lists seven and shows better timing. First investigate the missing clock and its endpoints. Do not celebrate the slack improvement until coverage is restored.

Original guide diagramThe design loads and timing looks clean. Why can the inputs still be wrong?
The design loads and timing looks clean. Why can the inputs still be wrong?, illustrating the physical design concept.