ExpertQuestion 160 of 161Source: Synopsys IC Validator User Guide: Output Files, Error Classification; Ansys RedHawk User Manual: Static IR/EM, PathFinder ESD Analysis; Synopsys ICC2 Implementation User Guide: RedHawk and RedHawk-SC Fusion

What is the final physical signoff gate, and who signs each item?

From PDVerse PnR Interview Handbook · pdVerse Mentor Guide

Short Answer

The physical gate proves that the exact GDS going to the fab is manufacturable and electrically sound. Full-chip DRC and LVS on the final merged GDS with the released runset, ESD and ERC checks, IR and EM signoff, and a reviewed waiver list must all be closed, each with a named owner. Timing is signed separately through the timing gate, which eco-final-signoff-gate covers.

Technical Reference DiagramWhat is the final physical signoff gate, and who signs each item?
A flow from the final merged GDS through full-chip DRC, LVS, antenna and density checks, ESD and ERC checks, IR and EM signoff, and waiver review to the tapeout package, with the owner of each gate named beside it.

Technical Explanation

  • DRC: RESULTS: CLEAN (ICV) in cell.RESULTS (ICV) from a full standalone run on the final merged GDS, with the released foundry runset. Antenna and density rules are part of that deck. Owner: physical verification lead.
  • LVS: LVS Compare Results: PASS (ICV) and DRC and Extraction Results: CLEAN (ICV) against the final netlist, including macros and IO. Owner: physical verification lead, with block owners for any black-boxed cells.
  • Waivers: every waived violation recorded in the error classification database with a reason and approver. IC Validator excludes waived violations from the rule counts, so the waiver list must be reviewed as a document. Foundry-rule waivers need foundry approval.
  • ESD and ERC: resistance checks with perform esdcheck (RH) and any ERC rules in the runset, owned by the IO or ESD team.
  • IR and EM: static and dynamic drop within budget for every power scenario, PG EM clean at the signoff temperature, and ramp-up analysis for gated domains. Owner: power integrity lead.
  • Thermal: hot-spot temperatures within limits and used as the EM temperature. Owner: power integrity or package team.
  • The tapeout package holds the final GDS or OASIS, the DRC, LVS and ERC reports with the waiver list, the IR and EM signoff reports, and whatever other collateral the foundry or customer asks for. Project lead signs once every item above has a named approval.

What To Check

  • That every result points at the same final GDS, by checksum or timestamp.
  • Runset and tech file versions against the foundry release.
  • Waiver list reviewed and approved line by line.
  • IR, EM and ESD reports for every required scenario.

Command Checks & Actions

IC Validator (icv)icv -i final.gds -c top drc.rs

Full-chip standalone DRC on the final merged GDS.

IC Validator (icv)icv -i final.gds -c top -s top.sp -sf SPICE lvs.rs

Full-chip LVS against the final netlist.

IC Validator (icv)cell.RESULTS

Header lines for DRC and LVS, attached to the signoff record.

RedHawk (redhawk)perform emcheck -mode all

Standalone PG EM check in all modes for the signoff run.

RedHawk (redhawk)perform esdcheck -rule esd_rules.txt

ESD resistance checks on the final data.

Healthy, Suspicious & Hard-stop Results

  • Healthy (illustrative): All gates closed on one GDS checksum, 14 waivers approved, worst dynamic IR 68 mV against 72 mV, EM worst 88%.
  • Suspicious (illustrative): One report generated on a GDS from the day before the last ECO.
  • Hard stop: Any gate without a named approver, RESULTS: NOT CLEAN (ICV) with unreviewed waivers, or LVS on a netlist older than the final ECO.

Common Mistake

The Trap: Collecting clean reports from several runs over the last week and calling it signoff. The LVS run predates a metal ECO by a day, and the ECO's floating via would have shown up in the run that was never repeated.

What The Interviewer Is Testing

  • Does the candidate insist every result comes from the same final GDS?
  • Knowing who owns each item and how waivers are approved.
  • Keeping the timing gate distinct from the physical gate.

Follow-up Question & Model Response

"A foundry DRC waiver is still pending on tapeout day. What do you do?"

Candidate Model Response: Do not tape out on an assumption. Ask the foundry for a decision with the exact violation data and context, and find out whether a fix is feasible in the remaining time, since many waiver requests concern small geometries that can be reworked. If the schedule must move, the project lead makes that call with the risk written down. Taping out with an unapproved waiver risks a mask set that the fab may reject or a yield problem later.

Practical Example

Tapeout Scenario: Tapeout of a 70 mm2 chip (illustrative): DRC CLEAN with 14 approved waivers, LVS PASS with extraction CLEAN, all 96 ESD bump pairs passing, worst static IR 34 mV against a 45 mV budget at 0.9 V, dynamic 68 mV against 72 mV, EM worst 88% at 110 C. One LVS report is dated before the final ECO, so LVS is rerun on the final GDS and passes before the project lead signs.

PnR Flow Mentor Guide

Read the complete 8-chapter PnR Flow Mentor Guide free on the web — library setup through placement, clock tree synthesis, routing, chip finishing, hierarchical implementation, and ECO, all the way to stream-out.

PnR Flow Physical Design Mentor Guide — eight chaptersPnR Flow Mentor GuideEight chapters, library setup through to stream-out. →